It's not really two pole so much as pole-zero compensation. After all, a two-pole compensator would result in at least a three-pole system, which is nontrivial to solve for best results. With a zero, you can hope to position it near an existing pole, to get some cancellation and improve risetime or somesuch.

Looking at the network alone, it has the same HF behavior as a miller cap, since when Xc2 << R2, the resistor disappears and it looks like two caps in series. It cuts off somewhere before DC, since it makes a second order high pass filter. If the time constants are staggered (i.e., Cp2 working into Rp, Cp1 working into Rb), there will be some lead/lag action. Note, of course, pure RC poles can never overlap, be complex or be in the right half-plane.

When the impedances of stages in an RC filter are close, the poles get pushed apart. A buffered RC-RC filter (i.e., RC--buffer--RC) has a critically damped response, which for a lowpass is:

H = 1 / (s^2 + 2zws + w^2)

where w is the angular cutoff frequency w = 1 / RC and z is zeta, the damping factor. (The highpass equivalent is s^2 H, where you can imagine the s factors as derivatives, hence the high-pass filter's other name, the differentiator -- under certain conditions.)

For the unbuffered filter, finite values of impedance result in an overdamped system (zeta > 1). Zeta is 1.205 for the case of decade-stepped impedance, i.e. R2/C2 = 10 R1/C1, which isn't too bad, and the component values are usually pretty reasonable. Zeta rises to 3.5 for equal impedances (R1 = R2, C1 = C2), which is pretty awful. (A butterworth filter has maximally flat frequency response, with damping coefficient sqrt(2) / 2 ~= 0.7071.) This gives you some idea of the poor performance that unamplified RC networks give.

A complete analysis of this circuit would result in lots of ugly terms. This is a poor example of a feedback circuit: the input is coupled to the output, so at very high frequencies, gain is positive (near unity), while at low frequencies it's very high (roughly 1 / h_oe), and negative (i.e., inverting). You get feed-forward and feed-back relations, and everything depends on Zin and Zload.

We can make some helpful assumptions:

- Assume the input is constant current. Such a circuit is usually found after a diffamp, which has a reasonably constant-current output.

- Assume the collector output is constant current. Same justification, and the CCS shown is also going to be a collector.

- The actual load will generally be R || C, but perhaps we can make the excuse that the capacitance can be lumped into Cp2, and R will be larger than Xcp2 for the frequencies we're interested in. Alternately, we can look at the circuit alone with no load, and assume it will act slower in a real circuit.

This results in a circuit that looks like:

- Current input

- Output is a voltage controlled current source, corresponding to the transistor's transconductance (gm = dIc / dVbe = Ic / Vth)

- Network between input and output

Note I've renamed Cp1 to C1 for simplicity. Same thing.

So now we can use good old Nodal Analysis to figure it out, among other approaches.

@ Vbe:

i_in = (Vbe - V2) / (1 / (C1 s)) + Vbe / Rpi

@ V2:

(Vbe - V2) / (1 / (C1 s)) = V2 / R1 + (V2 - Vo) / (1 / (C2 s))

@ Vo:

(V2 - Vo) / (1 / (C2 s)) + i_out = i_c

And

i_c = Vbe Ic / Vth

Where Ic is the quiescent current (remember, BJTs are exponential, so i_c depends on Ic) and Vbe is the AC base voltage. In fact, all these variables (Vbe, i_c, i_in, i_out, V2, Vo) are AC quantities.

Rearranging, we get the 3x3 linear equation:

Code:

```
[ C1 s + 1 / Rpi , -C1 s , 0 ] [ i_in ]
A = [ C1 s , -(C2 + C2) s - 1 / R1 , C2 s ] = [ 0 ]
[ -Ic/Vth , C2 s , C2 s ] [ -i_out ]
```

Which could be reduced to a 2x2 system since we aren't interested in V2, or 1x1 (i.e., a proper transfer function) since we want i_out.

Complete transfer function later...

Tim