I have tried to understand Sloanes Opti-MOS design (schematic
at http://www.sealelectronics.com/kits/index.htm), but I am
quite puzzled by one thing. We have a push-pull VA stage
directly driving an OPS with MOSFET source followers. As far as
I can understand, a push-pull VA stage creates a current
difference between the upper and lower half when a signal is
applied. That is, assuming perfect balance the same current
flows through both halves at the Q point, but if we apply a
positive input signal, the current will increase in the upper half
and decrease in the lower half. Unless I have misunderstood
so far, we get a positive difference current that must flow
somewhere (unless recent research has invalidated KCL 🙂 ).
However, there is nowhere for this current to flow, since there
the only possible paths are blocked by capacitors or MOSFET
gates. I have tried to simulate in SPICE to see if I have
misunderstood something, but I cannot get it to work in SPICE
either. That could be some mistake on my side, or some problem
with SPICE, but it makes me supsicious of the topology.
Most of Sloanes MOSFET designs in his power amp book do
not use source followers, but Szikloy pairs with BJT drivers.
In this case I understand better how it works, since the BJTs
"consumes" the difference current. Some of these amps have
essentially identical VA stages and there is no problem to get
these amps to behave as expected in SPICE.
It is probably me not understanging something, but I cannot
figure out where I am going wrong.
at http://www.sealelectronics.com/kits/index.htm), but I am
quite puzzled by one thing. We have a push-pull VA stage
directly driving an OPS with MOSFET source followers. As far as
I can understand, a push-pull VA stage creates a current
difference between the upper and lower half when a signal is
applied. That is, assuming perfect balance the same current
flows through both halves at the Q point, but if we apply a
positive input signal, the current will increase in the upper half
and decrease in the lower half. Unless I have misunderstood
so far, we get a positive difference current that must flow
somewhere (unless recent research has invalidated KCL 🙂 ).
However, there is nowhere for this current to flow, since there
the only possible paths are blocked by capacitors or MOSFET
gates. I have tried to simulate in SPICE to see if I have
misunderstood something, but I cannot get it to work in SPICE
either. That could be some mistake on my side, or some problem
with SPICE, but it makes me supsicious of the topology.
Most of Sloanes MOSFET designs in his power amp book do
not use source followers, but Szikloy pairs with BJT drivers.
In this case I understand better how it works, since the BJTs
"consumes" the difference current. Some of these amps have
essentially identical VA stages and there is no problem to get
these amps to behave as expected in SPICE.
It is probably me not understanging something, but I cannot
figure out where I am going wrong.
Christer,
You may have better luck with your simulation if you add a high resistance to ground (say 1-10 megohms) at either or both of the collector outputs in the Vas stage. Some simulators (like mine) do not work unless every current path in the circuit has an explicit ground reference, however slight.
Also, note that because this Vas stage has almost no collector loading, gain at this point is extremely high and the current needed to swing to the rails is extremely small. The gate charge requirement of the output stage and various leakage current paths existing in the real circuit can account for it.
At the risk of pegging the blowhard meter, I will go on to say that the downside to this kind of minimal Vas loading is that is that it can can leave you with a very nonlinear open-loop charactieristic. I would prefer to swamp it with some resistive loading to ground, as seen in other MOSFET designs such as the Pass/Thagard A75. Such loading can also help ensure closed-loop stability.
You may have better luck with your simulation if you add a high resistance to ground (say 1-10 megohms) at either or both of the collector outputs in the Vas stage. Some simulators (like mine) do not work unless every current path in the circuit has an explicit ground reference, however slight.
Also, note that because this Vas stage has almost no collector loading, gain at this point is extremely high and the current needed to swing to the rails is extremely small. The gate charge requirement of the output stage and various leakage current paths existing in the real circuit can account for it.
At the risk of pegging the blowhard meter, I will go on to say that the downside to this kind of minimal Vas loading is that is that it can can leave you with a very nonlinear open-loop charactieristic. I would prefer to swamp it with some resistive loading to ground, as seen in other MOSFET designs such as the Pass/Thagard A75. Such loading can also help ensure closed-loop stability.
To the extent that nothing consumes this difference
current from the VA stage, the open loop gain becomes
very high. I haven't looked to see if there is any resistive
loading to the output or ground from this stage, which
would limit gain, but even assuming that there is not, the
gain will still remain finite, as the Mosfets have input
capacitance, and the VA stage itself will respond to the
voltage output as if there were some loading.
As an aside, I have found that it is often helpful sonically
to load the VA stage with some resistance to ground,
even when it results in some degradation of distortion spec.
current from the VA stage, the open loop gain becomes
very high. I haven't looked to see if there is any resistive
loading to the output or ground from this stage, which
would limit gain, but even assuming that there is not, the
gain will still remain finite, as the Mosfets have input
capacitance, and the VA stage itself will respond to the
voltage output as if there were some loading.
As an aside, I have found that it is often helpful sonically
to load the VA stage with some resistance to ground,
even when it results in some degradation of distortion spec.
Joe and Nelson,
thanks for your prompt replies. Yes, I had tried with resistors
to ground, without success. However, I finally spotted an error
in my SPICE input, so the simulation works now, even without
the resistors. Now, what you two say is, I understand, that
except for leakage currents, the only load is indeed the
gate capacitances and the compensation caps. I did realise
we have this load, of course, but since it would make the
open loop gain so extremely frequency dependant it seemed too weird to me to be true. Now when I've got the simulation
running, it confirms that this is indeed the case. The difference
current is essentially proportional to the frequency all the way
from mHZ to MHz. This seems like a dangerous and wild design
to me. Not that my opinion is authorative, but I think I sense you two having similar feelings about it. I guess I would feel more
comfortable adding a resistive load that dominates the
capacitances, at least for the audible range.
Another question, while we're at it. I am also intrigued by the
local feedback to the cascodes in the VA stage. I suppose we
get a feedback here through the cascodes modulating the Vce
of the CE transistors, but this seems to go against the spirit of
using cascodes in the first place. Do any of you have any
opnion on this?
thanks for your prompt replies. Yes, I had tried with resistors
to ground, without success. However, I finally spotted an error
in my SPICE input, so the simulation works now, even without
the resistors. Now, what you two say is, I understand, that
except for leakage currents, the only load is indeed the
gate capacitances and the compensation caps. I did realise
we have this load, of course, but since it would make the
open loop gain so extremely frequency dependant it seemed too weird to me to be true. Now when I've got the simulation
running, it confirms that this is indeed the case. The difference
current is essentially proportional to the frequency all the way
from mHZ to MHz. This seems like a dangerous and wild design
to me. Not that my opinion is authorative, but I think I sense you two having similar feelings about it. I guess I would feel more
comfortable adding a resistive load that dominates the
capacitances, at least for the audible range.
Another question, while we're at it. I am also intrigued by the
local feedback to the cascodes in the VA stage. I suppose we
get a feedback here through the cascodes modulating the Vce
of the CE transistors, but this seems to go against the spirit of
using cascodes in the first place. Do any of you have any
opnion on this?
sam9
Slone has a book on high-power amplifier design that walks one through each stage of his design decisions. I'm not sure it specifically covers the Opt-MOS or not but it is close. I'm not knowledgeable or experienced enough to discuss the contents (at least not intelligently), but it sounds like you are. The fact that I got something out of the book at all shows it is readable at least.
It might be worth your time to find a copy. Amazon has it.
I also have noticed that Slone's designs derive from Doug Self except that Self seems to be anti MOSFET and Slone goes either way (MOSFET vs. BJT) depending on the application.
Slone has a book on high-power amplifier design that walks one through each stage of his design decisions. I'm not sure it specifically covers the Opt-MOS or not but it is close. I'm not knowledgeable or experienced enough to discuss the contents (at least not intelligently), but it sounds like you are. The fact that I got something out of the book at all shows it is readable at least.
It might be worth your time to find a copy. Amazon has it.
I also have noticed that Slone's designs derive from Doug Self except that Self seems to be anti MOSFET and Slone goes either way (MOSFET vs. BJT) depending on the application.
Speaking just for myself, I wouldn't go so far as to call the design "wild and dangerous," but I believe that the more you stress an amplifier, the more you are likely to hear of its open-loop character, so it should be as close to the closed-loop behavior as possible to maintain a consistent sonic illusion. This can get deep, but briefly, I think this kind of consistency can be more important subjectively than absolute distortion, or even whether the dominant distortion is odd or even order. IMOHO, of course. 
Also, the "cascode" connection you refer to isn't really that, although it does resemble it. I think it's there just to split the Vce across two devices instead of one, which in turn lets the designer specify a lower VceMAX (but otherwise better) transistor in that spot.
Also, the "cascode" connection you refer to isn't really that, although it does resemble it. I think it's there just to split the Vce across two devices instead of one, which in turn lets the designer specify a lower VceMAX (but otherwise better) transistor in that spot.
Sam9
I already have Sloanes power amp book, but the Opti-MOS is
not in it. It is probably a newer design of his, and interestingly
it does several things in the opposite way from what he strongly
recommends in the book. He does, however, have one or two
amps in the book that would raise the same question as the
Opti-MOS, I just hadn't bothered about these since they seemed
not interesting for my purposes. The Opti-MOS is interesting,
however, to contrast with the amp in Fig. 11.14 in the book,
which he considers the optimal design of those in the book.
It is true he goes through quite well how a power amp works
(OK, how a certain type of amp works, so Nelson will not feel
intimidated 🙂 ). Personally, I would have liked some math in
it, but often he at least puts you on the track to derive
interesting results yourself. He does not discuss the issues
in sufficient depth to answer the question I asked. Or to
put it differently, it is obvious, of course, that the answer
we seem to have settled on could provide an answer, but
to me it seemed not very reasonable that that should be the
whole answer. The truth seems now to be that this is indeed
the whole answer, strange as it may seem.
I already have Sloanes power amp book, but the Opti-MOS is
not in it. It is probably a newer design of his, and interestingly
it does several things in the opposite way from what he strongly
recommends in the book. He does, however, have one or two
amps in the book that would raise the same question as the
Opti-MOS, I just hadn't bothered about these since they seemed
not interesting for my purposes. The Opti-MOS is interesting,
however, to contrast with the amp in Fig. 11.14 in the book,
which he considers the optimal design of those in the book.
It is true he goes through quite well how a power amp works
(OK, how a certain type of amp works, so Nelson will not feel
intimidated 🙂 ). Personally, I would have liked some math in
it, but often he at least puts you on the track to derive
interesting results yourself. He does not discuss the issues
in sufficient depth to answer the question I asked. Or to
put it differently, it is obvious, of course, that the answer
we seem to have settled on could provide an answer, but
to me it seemed not very reasonable that that should be the
whole answer. The truth seems now to be that this is indeed
the whole answer, strange as it may seem.
Joe Berry said:
I don't think so, since these transistors can handle a Vce of
180V. There should be no need to split the voltage for this
reason. The power dissipation seems also quite low so this
should not be a reason to lower Vce either.
Quite true these are not true cascodes, since the base voltage
varies, but they sit in the same position as cascodes usually
do and I suppose one could view them as a kind of cascodes
that also provide feedback, through modulation of the base
voltage and, thus, Vce of the CE transistors.
I see from the schematic that the rails are +/-65V, which would be 130V to each device worst-case, so perhaps you're right that they serve another purpose here. However, it may also be that Sloane intended this as a scalable topology that could go up to say 400W/ch. In that case he would have to allow for rails as high as +/-90V, or more.
You've got a point there. Scalability could be an issue. However,
it is still interesting to consider why he uses this feedback design
rather than straightforward cascodes. I suppose local feedback
can be good (althoug Sloane himself used to speak against it 🙂 ).
On the other hand, a proper cascode would give better HF
properties, I suppose.
it is still interesting to consider why he uses this feedback design
rather than straightforward cascodes. I suppose local feedback
can be good (althoug Sloane himself used to speak against it 🙂 ).
On the other hand, a proper cascode would give better HF
properties, I suppose.
Slone
If all else fails, Slone does respond to e-mails and seems to be a very nice fellow, especially if you are trying to build one of his designs!
If all else fails, Slone does respond to e-mails and seems to be a very nice fellow, especially if you are trying to build one of his designs!
I agree with Nelson but my reason to load the VAS stage a little bit is that I feel more secure when I know the exact gain. The SEAL amp look very much alike the QRO amp I designed 1984, it's a standard solution I think.
The base voltage for the cascodes aren't so sensistive how this is done according to my own experience. You can do it in two ways:
Fixed voltage across R22-Q16-Q15 base
or between Q16, emitter - Q15, base.
The later is more right but the first works also. I haven't been able to test the exact difference. Somebody who has?
Casode in the VAS is a very good idea I think. Cost little and does much.
The base voltage for the cascodes aren't so sensistive how this is done according to my own experience. You can do it in two ways:
Fixed voltage across R22-Q16-Q15 base
or between Q16, emitter - Q15, base.
The later is more right but the first works also. I haven't been able to test the exact difference. Somebody who has?
Casode in the VAS is a very good idea I think. Cost little and does much.
peranders said:
Yes it is rather common if you have BJTs following the VAS.
Perhaps it is common also when driving MOSFETs directly with
no resistive load, but to me it seems quite a different thing in
this case. Perhaps there is not really such a big difference, but
with my limited skills in analysing circuits I feel uncomfortable
when things seem to "float" and rely on ill-defined or secodary
semiconductor parameters.
(Edit: I did some experiments with adding resistive loads to
the VA stage and simulated this. It seems the design is very
sensitive to such loads, with noticeable effects on open-loop gain
and frequency response even for very high resistances. )
The base voltage for the cascodes aren't so sensistive how this is done according to my own experience. You can do it in two ways:
Fixed voltage across R22-Q16-Q15 base
or between Q16, emitter - Q15, base.
The later is more right but the first works also. I haven't been able to test the exact difference. Somebody who has?
[/QUOTE]
Yes, but neither is the case in the Opti-MOS, since the base
voltage of the cascode transistor Q15 is always kept halfway
between the output and the rail. That is, it is not constant at
all but provides some kind of feedback. Or rather, I thought it
was some kind of feedback, but that seems not to be the case
either. I changed to a constant voltage at the base and simulated
this circuit. It turns out that almost all of the open-loop gain
was lost. I still haven't understood what is really happening
here.
Re: Circuit
Well, it is not very similar in my opinion. The VAS is followed by
BJT drivers, not MOSFETS, so we have something that can
be considered a resistive load (although non-linear). Further
it is not a push-pull VAS.
Perhaps it is just me thinking of this as a major difference, but
I find the Opti-MOS harder to analyse and understand and
I am left by a feeling of unease that I do not get from most
other designs.
carlmart said:
Well, it is not very similar in my opinion. The VAS is followed by
BJT drivers, not MOSFETS, so we have something that can
be considered a resistive load (although non-linear). Further
it is not a push-pull VAS.
Perhaps it is just me thinking of this as a major difference, but
I find the Opti-MOS harder to analyse and understand and
I am left by a feeling of unease that I do not get from most
other designs.
"The difference current is essentially proportional to the frequency all the way from mHZ to MHz. This seems like a dangerous and wild design to me."
It's industry-standard. Especially in op-amps. Overall feedback flattens the repsonse out again.
"I guess I would feel more comfortable adding a resistive load that dominates the capacitances, at least for the audible range."
Aren't capacitors just as worthy a load as resistors? Just depends whether you want to store energy or dissipate it.
It's industry-standard. Especially in op-amps. Overall feedback flattens the repsonse out again.
"I guess I would feel more comfortable adding a resistive load that dominates the capacitances, at least for the audible range."
Aren't capacitors just as worthy a load as resistors? Just depends whether you want to store energy or dissipate it.
There is a popular philosophy of limiting the open loop
gain at low frequencies so as to create a constant
gain figure across the audio band.
I don't subscribe to the importance of the concept of TIM,
but I have noted that limiting the gain via resistive loading
of VA stages does help impart a consistent spectral
character to the sound.
gain at low frequencies so as to create a constant
gain figure across the audio band.
I don't subscribe to the importance of the concept of TIM,
but I have noted that limiting the gain via resistive loading
of VA stages does help impart a consistent spectral
character to the sound.
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