push-pull smps funny observation

[zilog]

I have an smps prototype using the schematic in http://wintermute.csbnet.se/~zilog/schemat.jpg

I observe the waveform below on ISNS_OUT, but its the same at ISNS, except the smooth downslope - http://wintermute.csbnet.se/~zilog/smps_currwaveform_synthesized.jpg

1 div is full on-time for one primary phase, 1 div is 20A current. Is it normal that when one primary stops conducting, the current in the other phase continues where the other one left off, but then again it all begins at zero? I would expect to see sawtooths that return to zero, or the same level atleast between each conduction interval.

I suspect this causes the smps to duty cycle-limit at 60% given high load.

EDIT: the smps uses Average Current Mode Control

 

[sawreyrw]

It's pretty clear to me why 33 people didn't respond to this. Maybe if you make it legible, someone will help you.

 

[guitar_joe]

loving the coffee stains on his brutalised schematic.

can't really say i can offer any advice on your problem.

 

[zilog]

For some clarification, I have drawn a figure of how I think the waveforms should look like in a push-pull smps

An externally hosted image should be here but it was not working when we last tested it.

"A" and "B" is the time primary 1 respectively primary 2 are switched on, "C" is the average level the current reaches at equilibrium.

 

[zilog]

Got a random idea.

The output iductors are wound on a common core, could this phenomenon be caused by reversing the direction of one of the windings? I must check when I get the time.

 

[zilog]

I tried reversing the direction of one of the windings on the output inductor - no observable change in anything. Then I disconnected the B+ return wires for the clamping capacitors/diodes - efficiency dropped like a stone, but the current waveforms all went normal, sawtooths starting on the same current level for both primary phases.

Is there any special magic I have missed when it comes to lossless clamping and A-CMC? I guess the clamping scheme messes with the primary side current waveforms, looks like the core goes into saturation at certain voltages, but at 0.2 volt higher input, it looks normal when the clamping is connected - guess it also affects the control loop in some way.

Isnt Eva here somewhere to spread wisdom?

 

[zilog]

I rerouted the lossless clamping to go through the current sense transformers - suddenly the primary current waveforms became identical for both push pull-channels. 4 div == full on-time for one primary channel, i div vertical == 20A.

One problem remains however (for both directions of winding for the output inductor) - I get this output from my sense transformers (called ISNS in the schematic):

An externally hosted image should be here but it was not working when we last tested it.

I feed the smps 15.1V from a very capable PSU, and I cannot get the full output voltage from the smps, what strangeness am I observing here? What could possibly cause the dI/dt of the output inductor to change so sharply?

 

[zilog]

I have now rewound the mutually coupled inductor using half the Bmax compared with the last one, still no change in behaviour.

One funny thing though - I now get this reading from the combined signal from the CT:s (ISNS) -

An externally hosted image should be here but it was not working when we last tested it.

I dont think the reason for every second pulse to be higher is transformer saturation because the current doesnt rise exponentially towards the end of the on-period.

The main transformer has Ae = 125mm^2, 3 turns per primary, and each primary is turned on for a maximum of 9us, the input voltage is 15V at maximum which yields dB ~3900-4000G which should be fine.

Am I observing CT saturation?

 

[zilog]

I have now rewound the CTs using large 3F3 ferrites, the difference in peak current between the primaries is now almost gone, guess I miscounted the number of turns for the original CTs.

I do still have problems with getting high current from the smps, the controller gives 100% duty-cycle, still the output conducts current for maximum ~60% of the time, have a look at this picture: smps_output_and_input.jpg

It shows two traces: the voltage from the secondaries of the transformer, and the drain voltage of one of the primary switch transistors, low voltage means its conducting current.

It looks like it takes some time after the mosfets turn on until voltage is present at the input to the secondary rectifiers, If I look at the output from the current transformers I can also observe this behaviour as a current that initially rises fast (no voltage yet at the output of the transformer), and then changes slope halfway through the conduction cycle (now voltage becomes present on the transformer secondaries), see this picture: smps_curr_x_former.jpg

It seems to me like the main transformer "consumes" current to begin with, and until it has had a certain amount of energy, it wont function as a transformer. The core is of unknown ferrite, but it doesnt seem to go into saturation as it stays cold even at prolonged 150W power levels.

Could this have something to do with the transformer ferrite material? Should I try to get hold of some large gauge 3F3 just for a test?

 

[switchmodepower]

First thing fix those waveforms- they look just as sloppy as your schematic. They look horrible. Get rid of the ringing.

As far as those waveforms not being in sync. Measure across primary fet (as you have) and measure across pins 4-6 of xfmr. If the scope does not like it, measure fronm 4-5.

.

 

[zilog]

First thing fix those waveforms- they look just as sloppy as your schematic. They look horrible. Get rid of the ringing.

As far as those waveforms not being in sync. Measure across primary fet (as you have) and measure across pins 4-6 of xfmr. If the scope does not like it, measure fronm 4-5.

It's not the ferrite material.

The thing is veroboarded during prototyping - is it possible to even achieve clean waveforms with these currents on veroboard? The thing goes haywire above ~40A peak primary current.

Btw, the picture is for one of the primary fets, and pin 4-6 of the xfmr. The primary side does not have much ringing, but the secondary does. Note however that there is not even any ringing on the secondary during the first part of the on-period.

The schematic looks the way it does since the CAD program is so horrible to use, that I simply cannot stand using it..

 

[switchmodepower]

I wouldn't even attempt to hand wire on veroboard. Go right to a good pwb design- large gnd planes, low inductance traces, etc.. If you have to use flat foil whenever possible to reduce inductances. Component placement is the most important. Do you have a pic of the layout?

Just for a sanity check can you measure across 1-3 and 4-6. They should match up.

 

[zilog]

I wouldn't even attempt to hand wire on veroboard. Go right to a good pwb design- large gnd planes, low inductance traces, etc.. If you have to use flat foil whenever possible to reduce inductances. Component placement is the most important. Do you have a pic of the layout?

Just for a sanity check can you measure across 1-3 and 4-6. They should match up.

I have lots of more things that arent even designed yet, thats why I stay on veroboard. I might not be able to test the high power stuff, but I should at least be able to sort this power level out.

pin 1-3 and 4-6 do NOT match - the primaries have voltage for a heck of a lot more time than the secondaries have, this is what disturbs me.

Well, I have a newly wound transformer sitting on the table waiting for testing, just gotta find time to do it.

As for a picture of the setup, this is the most recent: setup

EDIT: horrible spelling due to epoxy on fingers

 

[switchmodepower]

Well 1 thing I see wrong is your transformer is optimized for high leakage inductance. I assume that large toriod is your transformer? If so you shouldn't have the windings split like that. No wonder why you have all of that ringing.

A toroid is probably not the best xfmr to use but if you want it it must be wound bifilar or layered on top of each other. Also you should really find out what material it is since you get get a 26mu mpp core or a high perm and they look the same.

And for your cs xfmr you should be using a high perm core like 10000u not 3F3- it will add error if you go to current mode.

Here is one mistake I made a long time ago that had me driving crazy. Make sure that the channels on the scope are sync'd- some scopes allow the channels to be offset in time. To test it just put both channels at the same point.

 

[guitar_joe]

yeah optimise the magnetic components for what purpose and frequency you are running. and optimise the winding of the transformers.

If do this it will improve the supply's performance and make it easier to track down problems.

 

[zilog]

Well 1 thing I see wrong is your transformer is optimized for high leakage inductance. I assume that large toriod is your transformer? If so you shouldn't have the windings split like that. No wonder why you have all of that ringing.

A toroid is probably not the best xfmr to use but if you want it it must be wound bifilar or layered on top of each other. Also you should really find out what material it is since you get get a 26mu mpp core or a high perm and they look the same.

And for your cs xfmr you should be using a high perm core like 10000u not 3F3- it will add error if you go to current mode.

Here is one mistake I made a long time ago that had me driving crazy. Make sure that the channels on the scope are sync'd- some scopes allow the channels to be offset in time. To test it just put both channels at the same point.

I just dont see how I should be able to wind the toroid in any other way - the wire is just impossible to bend, that's why I attach turn for turn using epoxy on the prototypes.

I have already made that mistake with the scope once - its checked and not happening now.

The CT:s are running very low volt*time products and inductande is reasonable high, and shouldnt add that much error, I have double checked using 3E25 ones, and no visual difference with the currents I run.

 

[guitar_joe]

just takes a bit of practice.

first transformers i wound were ei core ferrites. quite easy.

toroids are difficult to wind. If you are finding it hard to bend the wire just use a group of thinner strands of wire. It reduces lossess at high frequencies aswell. notably the skin effect...

 

[zilog]

just takes a bit of practice.

first transformers i wound were ei core ferrites. quite easy.

toroids are difficult to wind. If you are finding it hard to bend the wire just use a group of thinner strands of wire. It reduces lossess at high frequencies aswell. notably the skin effect...

I am using 6x0.6mm wires for the prototype. Guess I will aim higher for the "real" one some time in the future. You done have any guidelines on how I should arrange the windings? I see from other people's smps:es that my toroid looks quite different.

Should I space out the 3+3 primary turns to cover more degrees of the toroid, or should I split the primary windings into several 3+3 turns that cover different parts of the toroid, that are coupled in parallell through the PCB?

 

[guitar_joe]

The second sounds like the way to go for sure.
It will decrease esr losses and promote better coupling.

Just as long as it doesn't increase the flux density over using a single 3+3 primary.

That is a question someone else may be able to help you with!

 

[switchmodepower]

The key to reducing leakage and have better coupling is reduce the spacing between primary and secondary. You can add more wire but just use thinner. You can also add more windings in parallel. So instead of winding 1 winding qualfilar you can have several primarys using thinner wire and imbed prim/sec/prim/sec.

However, no matter how you wind do in a toroid, performance will always be better in an EI, EE,PQ, etc core, unless you are designing for resonant mode.