Push pull buffer bias

Hello everyone,

I have a question about the push-pull buffer below. It is biased by a voltage divider so it can be run from a single supply. Now there is a 100k resistor between the bases and the voltage divider, but suppose I want to increase the input impedance, is there an objection to put a 1meg resistor or even higher?

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There is no guarantee that Q1 and Q2 will have the same base current. So absval( Ib_Q1 ) - absval( Ib_Q2 ) flows in the 1 megohm bias resistor, and the input DC bias point is shifted away from half_rail by (deltaI * 1 megohm).

Another mechanism that shifts the input DC bias point away from half_rail is: tolerance of R1 and R2. Suppose R1 is (10K + 1%) while R2 is (10K - 1%) ; then the input DC bias point is 8.9100 volts instead of 9.0000 volts. An error of 90 millivolts.

Which is larger: the input DC bias point error due to (different base currents in Q1 and Q2), or the input DC bias point error due to (1% resistors for R1 and R2) ?
 
Thanks for your answer Mark,

I had noticed the shift from half rail when inserting a 1meg resistor in the simulator, but this can be solved by adjusting the voltage divider I thought. Or is there a catch?
Actually, If the base currents would be exactly equal, there would not be a current through the bias resistor, so could I make it as large as I want?
 
I just realized that R8 is very small, so you are going to have extremely poor frequency response in the bass region. Have LTSPICE run an AC analysis and plot the expression (V(OUT) / V(IN)) . Its bass response rolls off dramatically.

The standard cure is to change C2,3 and/or change R8. You want (C2 * R8) > 4E-2 seconds. Then run LTSPICE AC analysis again and plot the expression again. Aaaah. Better.
 
I just realized that R8 is very small, so you are going to have extremely poor frequency response in the bass region. Have LTSPICE run an AC analysis and plot the expression (V(OUT) / V(IN)) . Its bass response rolls off dramatically.

The standard cure is to change C2,3 and/or change R8. You want (C2 * R8) > 4E-2 seconds. Then run LTSPICE AC analysis again and plot the expression again. Aaaah. Better.
I made R8 small to see what the output impedance of the circuit is, and forgot to change it back to a more sensible value..
For a higher input impedance you can replace BJT for JFET too. Thus R3 may be several megOhms.
Yes, but complementary jfets are not so easy to source these days. Especially the p channel. So I wanted to see how high an input impedance I can get with BJT's.
 
I suspect you can easily achieve an input impedance greater than ten megohms with all-BJT circuitry, even when Q1 and Q2 don't have the same base current. The trick is to be old enough to remember landline telephone taps (highly illegal but lots of fun), and how they achieve very high input impedance.

The very first figure in the Wikipedia article shows a circuit easily adapted to post #1 of this thread.
 
This arrangement (AC coupling) is advantageous regarding small-signal linearity, but it does nothing for the large-signal compared to a single transistor biased by a 5K resistor: if the signal is large and the output load is heavy (100 ohm is pretty low), the capacitors will charge, and un-bias the transistors. You can certainly simulate it
 
So, I simulated the circuit with bootstrap as below, and it seems to work very well. Input impedance is about 1meg. Thanks Ed!

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This arrangement (AC coupling) is advantageous regarding small-signal linearity, but it does nothing for the large-signal compared to a single transistor biased by a 5K resistor: if the signal is large and the output load is heavy (100 ohm is pretty low), the capacitors will charge, and un-bias the transistors. You can certainly simulate it
The load will in practice be much lighter than 100 ohms. That was just a test to see about the output impedance.
 
There is no guarantee that Q1 and Q2 will have the same base current. So absval( Ib_Q1 ) - absval( Ib_Q2 ) flows in the 1 megohm bias resistor, and the input DC bias point is shifted away from half_rail by (deltaI * 1 megohm).

Another mechanism that shifts the input DC bias point away from half_rail is: tolerance of R1 and R2. Suppose R1 is (10K + 1%) while R2 is (10K - 1%) ; then the input DC bias point is 8.9100 volts instead of 9.0000 volts. An error of 90 millivolts.

Which is larger: the input DC bias point error due to (different base currents in Q1 and Q2), or the input DC bias point error due to (1% resistors for R1 and R2) ?
Then choosing very well matched resistors and no input base bias one could match the transistors by measuring the output dc offset...in this case , just half of a diamond buffer, the voltage on r4, r5.
 
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