Hello everyone,

I'm a newbie in amps design and I'm trying to design a power amplifier based on Bob Cordell's book "Designing Audio Amplifiers" designs.

The problem is I don't have the BUZ900P and BUZ905P models and I can't simulate with the referred devices.

I'm simulating with IRFP240/9240 pair, but I've got some problems, if I increase the Miller compensation capacitor (used to form a Miller integrator at high frequencies) I've a better phase margin, but the slew rate and THD gets worse.

I've also other components influencing this characteristics, the Zobel network which causes overshoot at frequencies if the value of Rz or Cz is to high, and there's also another problem, the gate stopper resistors used to "kill" parasitic gate oscillations, if the value is to low I've danger of oscillations and the phase margin is terrible, If I raise the value I've got again overshoot at high frequencies.

Inicially I tried to leave the power devices without quiescent current, something like a "pure" class B, and this results for the gain margin, but the overshoot it's huge.

I've tried to use Bob Cordell's formula of CMiller = gmLTP/(2*pi*fH*Acl) [F], but this formula seems to be wrong.

Attached is the circuit made in TINA and also two pictures of the circuit.

Thank you very much for your help,

Best regards,

Daniel Almeida

I'm a newbie in amps design and I'm trying to design a power amplifier based on Bob Cordell's book "Designing Audio Amplifiers" designs.

The problem is I don't have the BUZ900P and BUZ905P models and I can't simulate with the referred devices.

I'm simulating with IRFP240/9240 pair, but I've got some problems, if I increase the Miller compensation capacitor (used to form a Miller integrator at high frequencies) I've a better phase margin, but the slew rate and THD gets worse.

I've also other components influencing this characteristics, the Zobel network which causes overshoot at frequencies if the value of Rz or Cz is to high, and there's also another problem, the gate stopper resistors used to "kill" parasitic gate oscillations, if the value is to low I've danger of oscillations and the phase margin is terrible, If I raise the value I've got again overshoot at high frequencies.

Inicially I tried to leave the power devices without quiescent current, something like a "pure" class B, and this results for the gain margin, but the overshoot it's huge.

I've tried to use Bob Cordell's formula of CMiller = gmLTP/(2*pi*fH*Acl) [F], but this formula seems to be wrong.

Attached is the circuit made in TINA and also two pictures of the circuit.

Thank you very much for your help,

Best regards,

Daniel Almeida

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