Excuse me! I overlooked the schematics. Those driver can be adequate. But I think the problem comes from cross-conduction or body diode reverse recovery. There isn't another high-current path in the circuit.
I think what you should start with is a good look at the gate waveforms... they'll pretty well tell you everything you need to know about what's going on.
Secondly that mosfet is an excellent choice but needs a bit of care with respect to delays, especially with this type of driver.
Your choice of transistors are perhaps less than optimal in the driver, you may consider changing them.
There's several ways to tweak delays, "dead time" and driver gain in this circuit, you better know them all.
Once you have that nailed down then you can worry about fixing up the overcurrent circuit. Right now you're still at the blowing mosfet testing phase.
With a fairly simple circuit you could easily disconnect the comparator outputs to the driver, and trigger the drivers with a signal generator of some sort.
Secondly that mosfet is an excellent choice but needs a bit of care with respect to delays, especially with this type of driver.
Your choice of transistors are perhaps less than optimal in the driver, you may consider changing them.
There's several ways to tweak delays, "dead time" and driver gain in this circuit, you better know them all.
Once you have that nailed down then you can worry about fixing up the overcurrent circuit. Right now you're still at the blowing mosfet testing phase.
With a fairly simple circuit you could easily disconnect the comparator outputs to the driver, and trigger the drivers with a signal generator of some sort.
How do I measure gate waveforms? when I connect the probe (even with a common mode choke on the probe line), I get no waveform at all (well, some noise with 50mv p-p), my equipment seems to be too crapy and I am too poor to fix this shortcoming. The scope is a Tektronix 2225 with 50 MHz bandwidth, and the probes 10MOhm/11pF, 1.5 ns 10X.
My choice of bipolar transistors is dictated by what ELFA (the only company that I know of in sweden that sells components) offers. These (2N5551, 2N5401) their only >100V choices, getting components from abroid is simply way over the budget I am willing to accept for this project.
Do you have any guide for learning how to set deadtime etc? I believe this actually might be a version of your circuit that I selected values for in LTSpice to get working with my component choice. Right now I am completely off the Spice values since the models that I used seem to be completely inadequate.
I have tried changing R2/R4 until the UcD simply can no longer switch, even then I get shoot through.. and I use 220 ohm for R6/R7 now, even that makes no difference other than enormous amounts of heat in my output devices. If I could get some better transistors for T1/T2 I would like to try them, but I am quite limited in my choice here.
My choice of bipolar transistors is dictated by what ELFA (the only company that I know of in sweden that sells components) offers. These (2N5551, 2N5401) their only >100V choices, getting components from abroid is simply way over the budget I am willing to accept for this project.
Do you have any guide for learning how to set deadtime etc? I believe this actually might be a version of your circuit that I selected values for in LTSpice to get working with my component choice. Right now I am completely off the Spice values since the models that I used seem to be completely inadequate.
I have tried changing R2/R4 until the UcD simply can no longer switch, even then I get shoot through.. and I use 220 ohm for R6/R7 now, even that makes no difference other than enormous amounts of heat in my output devices. If I could get some better transistors for T1/T2 I would like to try them, but I am quite limited in my choice here.
zilog said:
I understand your situation regarding part selection, when I built my amp it was dictated mostly by whatever junk I could scavenge from at times.
However it often comes down to having to use what will work. The choice of transistors is not that bad though. One thing is certain, your choice of baker clamp diode is less than optimal, and this is a make it or break it component from my experience. You need something with very little capacitance, have a look at the bat54 or equivalent instead.
Alternatively you can use a dual diode-non schottky version which would be more robust against component selection and temperature variation. I'd posted my version of that several times so you just need to find it. That also helps guard the turn on transistor from high Vcb and allows you to get away with a small signal turn on transistor, as does the cascode btw, you just don't need a 100V transistor for this.
What you need to use the simulator for is to gain an understanding how it all works as a system. There are many interractions that come into play and that's what you have to learn in order to optimise it, it will not serve to find you finalized values, as you've seen.
One downfall of these drivers is that they're easily loaded down. This is made less likely with an efficient mosfet such as you're using but it's something you need to be weary of during the optimisation process. That's to say, without understanding how the interractions work there's a very good chance that ~50mV worth of noise is all you're actually getting out of the drivers. Even a DMM will tell you if they're loaded to that extent, have a look across the bootstrap cap for instance.
There's obviously nothing here providing you with a given "digital" type of dead time delay. Rather you're at the mercy of the components to provide you with proper switching behavior, this includes gain, bandwidth (small signal works great in the drivers 2n3906, 2n4401, 2n2907...BCXXX).
Use their characteristics to your advantage in order to create gate-source waveforms that provide you with the proper natural "soft" dead time. That should look something like a turn on slope that's twice as gradual as the turn off slope, with intersections somewhere around Vth, for minimal dead time induced distortion, yet enough natural delay to allow the body diode to recover.
Try to keep the series gate resistor reasonable, say between 10 and 100 ohms, and you really can't neglect the fact that the value of the current mirror's "balance" resistor is what sets the level of current output to the drivers.... thereby setting their gain, and affecting the level of soft dead time as well.
Now you can start to see the limitations of this basic driver and why it's only good for lower power in this form (you're pushing the limits with it), but you can also see it's more than adequate given the fact that this is not an open loop "true digital" type of amp but a self oscillating one 🙂
BTW, if you can't use your scope..... can I have it ???
To avoid making new errors - will transistor selection 2N3906 and baker clamp diode BAS81 do (fits my PCB better than a BAT54)? The BAS81 diode seems to have even lower diode capacitance than BAT54 (I guess this dictates the reverse recovery time?)
Yeah that's the idea behind the capacitance.
Can't tell you if that's going to be your final solution, you're the one with the scope after all 🙂 Seems like it's worth a shot though. I've used that transistor with success but not at these voltage levels (whatever they are).
Trust your scope.
Can't tell you if that's going to be your final solution, you're the one with the scope after all 🙂 Seems like it's worth a shot though. I've used that transistor with success but not at these voltage levels (whatever they are).
Trust your scope.
classd4sure said:
The amplifier both works fine and sounds fine (without excessive heat at any power level) - so I dont trust my scope. Although tomorrow I will receive the mother of all toroids that I have ordered to filter my probe - so hopefully I will be able to measure gate waveforms without.. I will also receive the new diodes and transistors.
I have not much heat, my problem is that my current sense circuitry gets triggered by cross conduction in the output stage, but I very much suspect most of the problem to be in my measurement equipment (I dont know if the scope shows the real signal or just common mode switching noise). My aim to solve this problem is to minimize cross conduction since this probably also needs to be done - at least it wont hurt. The bootstrap circuit gets the rated 13 volts (will try to minimize this to 10-11 since its excessively high), and the heat sink gets hottest in idle and coldest during full clipping into 4 ohm, where switching frequency is at its lowest. The switching waveforms are also completely square and without ringing in idle, but picks up ~20% ringing at full drive. So I suspect I still have too much cross conduction.
Yesterday I made a mistake and delayed the wrong edge of the drive waveforms applied to a typical class-D output stage (thus causing the opposite effect to dead time). Result: 100ns cross-conduction and 2Vp-p spikes happily picked up by my oscilloscope probes as soon as I placed them near the (idle with 0V 0A output) circuit, even with tip and ground shorted and not connected to anywhere. No noticeable excess heat was produced as a 100ns pulse just excites all the leakage inductances of the circuit and makes them radiate EMI like hell without producing destructive currents. Now with proper dead time the best that I can pick up in the same conditions is 50mVp-p.
Concerning common-mode filtering, you don't need a huge core as ferrites are mostly resistive at RF and the efficiency of the filter is just proportional to the number of turns and doesn't depend too much on the size of the core. You can't accomodate too much turns in a huge core without using a lot of probe wire. Mine have just the required inner diameter to allow wrapping the wire around them without removing the connectors. Also, I hope that you picked up a suitable core material.
Concerning common-mode filtering, you don't need a huge core as ferrites are mostly resistive at RF and the efficiency of the filter is just proportional to the number of turns and doesn't depend too much on the size of the core. You can't accomodate too much turns in a huge core without using a lot of probe wire. Mine have just the required inner diameter to allow wrapping the wire around them without removing the connectors. Also, I hope that you picked up a suitable core material.
Eva said:
I picked the largest core of 3E25 material I could get at the local store (incidentally, this is the smallest size I can squeeze my probe through 😉)
May I ask what Vgs you think I should peak at using FDP3682 transistors? Should I go for a lower voltage with higher resistivt losses at turn on and gain turn on/off speed, or go for full saturation?
Finally, do you have any suggestions to how I should connect my scope to look at the gate waveform of the high side driver? If I connect the probe (10 turns wound around a giant E-core of 3C85 material I found) ground to source of the high side, I immediately get failure in the digital displays in my lab supply (the go crazy and display absurd random currents/voltages etc), and the amp seems to change switching frequency quite radical, which leads me to suspect that this presents quite a good antenna/load to the test point.
Even 10 volts will have them well enchanced, driving them harder will only produce more turn off delay, which could also be beneficial.
classd4sure said:
One thing on this theme that comes to mind - say I have a gate drive supply voltage of 13V, but during idle (500 kHz) my Vgs only has time to reach 5V, if I increase load on the amplifier then, my switching frequency drops, and allows Vgs through its increased on-time to reach above 5V. Wouldnt this lead to increased shoot-through in addition to reverse recovery problems during high load?
That theory seems to be somewhat plausible. However I find it unlikely. At 5Vgs the mosfets would be extremely hot due to being ~half enchanced.
Try experimenting with Rb, your deadtime, rise/fall, slews etc are definitely off.
Try experimenting with Rb, your deadtime, rise/fall, slews etc are definitely off.
zilog said:
If you take a look at the datasheet, you will see that Rds-on is already below 0.1 ohm for Vgs=5V, below 0.05ohm for Vgs=6V and it does not improve too much for Vgs=10V and Vgs=20V. This leads me to think that a good compromise would be around 7V or 8V
Concerning the filter, it seems that you have a DC path between the ground of the oscilloscope and the ground of the lab power supply (or any other thing connected to the amplifier) that is causing DC to flow and saturating the core. Are all appliances earthed? All but one of them should be left floating. Once you get it to work you should see little or no change in the output of the amplifier. Are you sure that you are using enough turns? Also, be aware that any contents of the output of the amplifier (including the low frequency audio content) will be applied to the core, so it's quite easy to saturate it.
Eva said:
That kind of Vgs leaves very little margin. The bootstrap cap will sag during extended on time for instance, could easily end up changing Rdson by an order of magnitude or a few. Can't be a good thing right?
I think 10V is as low as I'd feel comfortable with anyway, and the usual 12V supply will do nicely.
I have finally got my measurement rig set up so I could measure the individual high and low side Vgs waveforms. The low side peaks at 5.5V, and the high side at ~10V. Is this difference in Vgs, and Vgs rise speed between high and low side normal, or should I perform some engineering to equal it out? I guess the modulator adjusts pulse widths to compensate, but the turn on/off will be assymetrical.
That could be a sign of the drivers being somewhat loaded as well.... and/or an incorrect Rb.
I'd definatly want them "="
I'd definatly want them "="
I now have a working setup where I can trace Vgs for both output devices. I have tried all thinkable combinations of anything important in the circuit (different turnoff-speeds, turn-on slopes, crossing levels for Vgs etc), but I still get roughly the same current spikes in the output stage. I measure these spikes over an inductance free sense resistor (winding-free 47 mOhm), and I end up with 8-10A with no signal in, and ~120A with full signal in.
These current spikes are too narrow to be more visible than thin lines on my 50MHz scope, but they contain enough energy for me to be unable to filter them out using RC-nets. I cant think of them being caused by anything else than reverse recovery, but howcome they are still the same no matter what gate resistor value or gate drive voltage waveform I use? They surely cant be caused by cross conduction since I now let my mosfets cross at ~0.5V, and the Vgs waveforms are all nice and smooth even at the crossings.
I would appreciate if you with working UcDs could perform the same measurements in your setups, and tell me what current waveforms that are normal in the output stage, since I have
exhausted all means I know of to affect this curcuit.
Btw, the time it takes to go from ~11V to ~0V Vgs is now 75 ns, is this a proper value or should I look for more exotic transistors to perform this function? At the same time I let the turn-on take several times longer.
These current spikes are too narrow to be more visible than thin lines on my 50MHz scope, but they contain enough energy for me to be unable to filter them out using RC-nets. I cant think of them being caused by anything else than reverse recovery, but howcome they are still the same no matter what gate resistor value or gate drive voltage waveform I use? They surely cant be caused by cross conduction since I now let my mosfets cross at ~0.5V, and the Vgs waveforms are all nice and smooth even at the crossings.
I would appreciate if you with working UcDs could perform the same measurements in your setups, and tell me what current waveforms that are normal in the output stage, since I have
exhausted all means I know of to affect this curcuit.
Btw, the time it takes to go from ~11V to ~0V Vgs is now 75 ns, is this a proper value or should I look for more exotic transistors to perform this function? At the same time I let the turn-on take several times longer.
I can't talk particularly about UcD since I'm working in my own class D designs, but when the cicruit is idle and inductor current is crossing zero during every switching period there are no diode reverse recovery events at all, and thus there should not be any spikes. At least, that's the (logical) behaviour that my circuits show. In these circumstances, any spike is telling you that one MOSFET is turning on while the other is not showing high impedance (be aware that in practice MOSFETs suffer from small current tails due to charge being stored deeply in the gate structure and then gate internal resistance preventing fast extraction). Also, you may be suffering from parasitistic turn-on Vgs spikes after turn-off.
Concerning the switching times, longer switching events produce less EMI at the expense of more heat, so I would use dissipation as the main criteria to adjust gate resistors. 75ns may seem a bit long for current standards, but if it does not produce too much heat, then it's fine (as the rest of consequences of going slower are all advantageous).
Concerning the switching times, longer switching events produce less EMI at the expense of more heat, so I would use dissipation as the main criteria to adjust gate resistors. 75ns may seem a bit long for current standards, but if it does not produce too much heat, then it's fine (as the rest of consequences of going slower are all advantageous).
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