I tried to post the pdf data file, but rejected because too big.
See Digi-Key - 917-1005-6-ND (Manufacturer - EPC1011)
Is this significant for ClassD development? Not sure how to mount one of these, though. Price isn't bad at all....
data sheet link:
http://epc-co.com/epc/documents/datasheets/EPC1011_datasheet_final.pdf
See Digi-Key - 917-1005-6-ND (Manufacturer - EPC1011)
Is this significant for ClassD development? Not sure how to mount one of these, though. Price isn't bad at all....
data sheet link:
http://epc-co.com/epc/documents/datasheets/EPC1011_datasheet_final.pdf
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Looking promising, but their casing design is really not developer friendly.
Also I wish they would have specified their body diodes more precise, or can it be true that their body diode really has a reverse recovery charge below the nC range?
Also I wish they would have specified their body diodes more precise, or can it be true that their body diode really has a reverse recovery charge below the nC range?
...have to correct myself...
It isn't a casing. It's a die.
Even I would love to change my current plans -
I tend to say: 'No problem' = No, I cannot. It's a problem.
It isn't a casing. It's a die.
Even I would love to change my current plans -
I tend to say: 'No problem' = No, I cannot. It's a problem.
Well that's the figure for the 200V 12A switch as well, so I don't think it's a mistake.
I think to really get out of these what is possible you can't put it in a case, especially for the price.
I think to really get out of these what is possible you can't put it in a case, especially for the price.
Well, for class D in the range of some single kW and switching frequencies up to 1 MHz, I could survive with TO-220 and would love TO-252 (D-pack). The resulting inductances can be handled without to much headache.
But the body diodes of Si-MosFets are a torture for my naive soul, and placing a series schottky + additional fast freewheeling is also not charming at all.
But the body diodes of Si-MosFets are a torture for my naive soul, and placing a series schottky + additional fast freewheeling is also not charming at all.
According to the docs in their "Tools and Design Support" pages,
http://epc-co.com/epc/documents/product-training/Appnote_GaNfundamentals.pdf
"With zero bias gate to source, there is an absence of electrons under the gate region. As the drain voltage is decreased, a positive bias on the gate is created relative to the drift region, injecting electrons under the gate. Once the gate threshold is reached, there will be sufficient electrons under the gate to form a conductive channel. The benefit to this mechanism is that there are no minority carriers involved in conduction, and therefore no reverse recovery losses. While QRR is zero, output capacitance (COSS) has to be charged and discharged with every switching cycle. For devices of similar RDS(on), GaN transistors have significantly lower COSS than silicon MOSFETs. As it takes threshold voltage to turn on the GaN transistor in the reverse direction, the forward voltage of the “diode” is higher than silicon transistors."
So apparently QRR is actually zero (not that I actually understand why).
There is another doc, http://epc-co.com/epc/documents/product-training/Using_GaN_r4.pdf that shows some circuit board patterns for using the parts. Apparently the solder-balled chip "package" can be soldered down using SMT techniques, though heatsinking doesn't look easy to accomplish (but efficiently coupled once done).
The rather low maximum Vgs rating is also intimidating. I imagine there will be a small jar of burned out devices resulting before an acceptible design is reached, at least by someone like me...
http://epc-co.com/epc/documents/product-training/Appnote_GaNfundamentals.pdf
"With zero bias gate to source, there is an absence of electrons under the gate region. As the drain voltage is decreased, a positive bias on the gate is created relative to the drift region, injecting electrons under the gate. Once the gate threshold is reached, there will be sufficient electrons under the gate to form a conductive channel. The benefit to this mechanism is that there are no minority carriers involved in conduction, and therefore no reverse recovery losses. While QRR is zero, output capacitance (COSS) has to be charged and discharged with every switching cycle. For devices of similar RDS(on), GaN transistors have significantly lower COSS than silicon MOSFETs. As it takes threshold voltage to turn on the GaN transistor in the reverse direction, the forward voltage of the “diode” is higher than silicon transistors."
So apparently QRR is actually zero (not that I actually understand why).
There is another doc, http://epc-co.com/epc/documents/product-training/Using_GaN_r4.pdf that shows some circuit board patterns for using the parts. Apparently the solder-balled chip "package" can be soldered down using SMT techniques, though heatsinking doesn't look easy to accomplish (but efficiently coupled once done).
The rather low maximum Vgs rating is also intimidating. I imagine there will be a small jar of burned out devices resulting before an acceptible design is reached, at least by someone like me...
Here is a diagram (from their powerpoint presentation on the website) of how board connection/heatsinking is done. You push the heatsink right against the (insulated) silicon back substrate. I guess that's not too far off from how Pentium chips are heatsinked, maybe doable by DIY.
....hm... I am already at my biological limit, when soldering a LT1711, but this would be definitely one step beyond.
Might be possible to get it running for some measurements to satisfy curiosity, but I doubt, that my DIY handling would result in a reliable construction.
Nevertheless - temptating.
Might be possible to get it running for some measurements to satisfy curiosity, but I doubt, that my DIY handling would result in a reliable construction.
Nevertheless - temptating.
A good challenge for the DIYer would be arranging to have the substrate surface all in a plane after soldering for compatibility with a hard thermal interface. Maybe if you were only losing a few watts per transistor, maybe normal for switching applications, a pad of some kind could be reliably used. The CPU analogy is good in the sense that it's a mammoth die (or four) only losing tens of watts peak each. Maybe a board house capable of handling flip chips at all would be able to handle decent coplanarity, but the usual surface mount equipment couldn't do it.
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Maybe if the thermal interface was to a floating heatsink, pulled against the substrate by some low spring force?
edit: I guess that would mean a separate heatsink for each chip. Probably not a good idea
edit: I guess that would mean a separate heatsink for each chip. Probably not a good idea
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You may have good luck using a thermal adhesive to bond and thin sheet fin to the die for test purposes, but anything other than a compressive load would probably bust it apart.
Yeah, bwaslo, like the conventional CPU plan. Worst case you'd have to do a little sink for each die.
I wonder how much of a thermal interface you'd get from the chip right to the board itself? The ICEpower boards use SOT mosfets with NO heatsink and seem to get away with it.
edit: the ASC200 boards, that is. Other modules are less adventurous about that.
edit the edit: make that the 200ASC boards.
edit: the ASC200 boards, that is. Other modules are less adventurous about that.
edit the edit: make that the 200ASC boards.
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I could also imagine that thermal coupling through a soft thermal gap filler pad might be sufficient.
It all depends on where you want die temperature. You could make a Kapton printed circuit and clamp it into a sink with rubber/glass pads on both sides, or even graphite if you masked everything. Getting the signal and power around it all in a decent way. Yikes.
Well, I believe these high-electron-mobility devices are just variations of microwave transistors and adapted to switched mode power. Still if you dig their docs, the demanded gate inductance is to be <2nH and Vgs never exceeding 6V for ~2.5V threshold. This calls for some serious RF-layout techniques and from this point of view I find the case quite friendly, you can try soldering that by reflow, infrared or even hotair.
just looked on their site, they now have a demo board available that looks like it might be tweaked into being a class D amp with some extra circuitry and without too much trouble. I haven't built a class D before other than mounting modules, so can any experienced builders comment on whether that might work? Thinking something like a UcD topologyhttp://epc-co.com/epc/documents/guides/EPC9002_qsg.pdf
I'm not sure if I missed something.
The figure 2 (Id vs Vgs) of the document shows great linearity.
If that graph is truly plotted using test data instead of just being an illustration skatch, I think this MOSFet might be great for linear operation too, I.e. Class A/AB amps
The figure 2 (Id vs Vgs) of the document shows great linearity.
If that graph is truly plotted using test data instead of just being an illustration skatch, I think this MOSFet might be great for linear operation too, I.e. Class A/AB amps
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