I will be the first to admit that the PLL circuit as well as the LPF in the schematic is not of my design. It is copied from Mark Heijligers' DAC, although implementation is different. 
To be put to use, it needs, however, to have it's LPF recalculated. The operation frequency of the original circuit is 705KHz, I want mine to operate at 2.8224MHz (64*44.1KHz, SCK output of CS8412).
To recalculate the PLL 3rd Order Passive Loop Filter, I need the following 7 arguments, and I was hoping some members on this forum could help me out..
They are:
To be put to use, it needs, however, to have it's LPF recalculated. The operation frequency of the original circuit is 705KHz, I want mine to operate at 2.8224MHz (64*44.1KHz, SCK output of CS8412).To recalculate the PLL 3rd Order Passive Loop Filter, I need the following 7 arguments, and I was hoping some members on this forum could help me out..
They are:
- Maximum output frequency from the VCO
- Desired bandwidth of the PLL
- Reference frequency of the loop (I guess this will be the 2.8224MHz...)
- Desired phase margin of the PLL (degrees, 30-70)
- VCO tuning voltage constant (MHz/Volt)
- Phase detector/charge pump constant (mA/2*pi*rad)
- Desired attenuation from the low pass filter (dB)
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The VCXO to be used is a Tent VCXO... 11.2896MHz... divided down to the 2.8224MHz used in the PLL.
