Phase margin with capacitive load

Hi

I simulated the amp Blameless-D.Self (output EF), with a load of 8R//100nF and the amp has overshoot with this load after measuring the Loop Gain and noticed that it is not PM <180° (Attached).
I am using in the output inductor with a shunt resistor (1uH-10R), output emitter follower, has no stability in capacitive load ?
The simulation is correct :scratch:, anyone have any comments...

Thanks
 

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Bonsai

Member
Paid Member
2003-07-25 10:44 pm
Europe
www.hifisonix.com
A few things you need to attend to here to improve your situation:-

1. you are running your LTP at far too low current. run it at minimum of 3mA - I prefer 10mA, but some people would say this is too high. 5mA is a good compromise.
2. The current source load in the VAS stage is far too low - you need to set this to about 30mA (on a triple emitter follower, you can get away with 15mA).
3. You need to add some emitter degeneration to your VAS transistor - you cannot run the VAS transistor like you have it without serious problems. Try about 33 Ohms to start off with.
4. I cannot read the value of your LTP mirror load resistors, but they look like 82 Ohms. These need to be about 22 Ohms each.