PD0052 and 18M432-D300 parts needed for 3 box DAC design

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The 18M432 D300 was manufactured by Fujitsu; however it’s been long out of production.

Attached is a PDF of the basic workings of the device. An interesting feature of its design is the use of Ceramic resonators – which give poor long term stability, however very good short term (low phase noise). The lack of long term stability is not a great issue of concern in a PLL type circuit. The advantage of Ceramic resonators is that fact they can be “pulled” (adjusted) over a very great range – I seem to recall Fujitsu claiming +/- 1000ppm!

Does anybody still have the Datasheet / Info on the 18M432 or the Fujitsu Varicap Diode FC54M?

Cheers,

John
 

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jean-paul said:
I have a new PD0052 for trade with other chips. Do you have a datasheet for it ??

I have the following brand new unsoldered chips, do let me know if you like to exchange for any of the below with your PD0052.


PCM1738E
24-Bit,96kHz Sampling Advanced Segment,Audio Stereo D/A Converter

DIR1701
a digital audio interface receiver (DIR) which receives and decodes audio data up to 96 kHz according to the AES/EBU, IEC958, S/PDIF, and EIAJCP340/1201 consumer and professional format interface standards.

CS5396
a complete stereo analog-to-digital (A/D) converters for digital audio systems. They perform sampling, A/D conversion, and anti-alias filtering, generating 24-bit values for both left and right inputs in serial form at sample rates up to 100 kHz per channel.
 
JohnW said:
The 18M432 D300 was manufactured by Fujitsu; however it’s been long out of production.

Attached is a PDF of the basic workings of the device. An interesting feature of its design is the use of Ceramic resonators – which give poor long term stability, however very good short term (low phase noise). The lack of long term stability is not a great issue of concern in a PLL type circuit. The advantage of Ceramic resonators is that fact they can be “pulled” (adjusted) over a very great range – I seem to recall Fujitsu claiming +/- 1000ppm!

Does anybody still have the Datasheet / Info on the 18M432 or the Fujitsu Varicap Diode FC54M?

Cheers,

John


Great explanation.
Is the 18M432 available in Hong Kong?
 
I've never seen them in HK / China, about 10 years ago I had a couple of Pcs, but I could not find them in my Lab here in HK, I will search my Labs in Paris and CZ in the next month - but Pls. don't hold your breath...

The only units I've seen the device used in is the old Teac external DACS - also used IC you requested, So I guess your working with a TEAC circuit.

John
 
JohnW said:
I've never seen them in HK / China, about 10 years ago I had a couple of Pcs, but I could not find them in my Lab here in HK, I will search my Labs in Paris and CZ in the next month - but Pls. don't hold your breath...

The only units I've seen the device used in is the old Teac external DACS - also used IC you requested, So I guess your working with a TEAC circuit.

John


Thanks for the searching.
I have not seen the TEAC circuit, but I believe it shoud be quite similar.
My design is as such :-
Control voltage input of the 18M432 is an 74HC4046 and the output is feed to the XT1 of the NPC SM5842AP digital filter.
 
rfbrw said:



Have you considered using two individual VCXO's ?

Yes, but not at this moment. I would want to keep it simple from now, get this project working and then improve from there.


BTW, are you referring to the below for the two individual VCXO's concept?


"A clock pulse generator system for providing a highly stable clock signal consists of two separate redundant clock signal generators which are controlled to operate in dead synchronization with each other. A microprocessor controlled digital phase lock loop operates to control each of the two clock signal generators and selects among a plurality of operating states such that the average dynamic phase difference in the two clock pulse signals generated is practically zero. Furthermore, the instantaneous dynamic phase difference does not exceed the phase noise of the voltage controlled crystal oscillators of the phase lock loops and, in one embodiment, is normally less than ten pico seconds, each phase lock loop comprising means for performing a fine, as well as coarse, phase comparison among internally or externally generated reference signals, only one of which is the highly stable clock signal output."
 
ec1288 said:


Yes, but not at this moment. I would want to keep it simple from now, get this project working and then improve from there.


BTW, are you referring to the below for the two individual VCXO's concept?


"A clock pulse generator system for providing a highly stable clock signal consists of two separate redundant clock signal generators which are controlled to operate in dead synchronization with each other. A microprocessor controlled digital phase lock loop operates to control each of the two clock signal generators and selects among a plurality of operating states such that the average dynamic phase difference in the two clock pulse signals generated is practically zero. Furthermore, the instantaneous dynamic phase difference does not exceed the phase noise of the voltage controlled crystal oscillators of the phase lock loops and, in one embodiment, is normally less than ten pico seconds, each phase lock loop comprising means for performing a fine, as well as coarse, phase comparison among internally or externally generated reference signals, only one of which is the highly stable clock signal output."


Err,no. I was thinking of something somewhat simpler and alot more common. Usually when external sync to a number of possible sources is needed two or three VCXO's are used to cover all frequencies.
BTW, I've seen a number of schematics using VxxMxxx devices and from what I remember of the PCM1732 demoboard (two VCXO's, 22.5792 and 24.576 MHz) and my experience of PLL equipped devices, with and without external sync, there is arguably very little difference, in terms of circuit complexity. Afterall the VxxMxxx devices are only multiple oscillators in a single package.
 
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