Hi - I have a technical question I have not been able to find a satisfying answer for trawling the forum archives.
I am working on a parallel PCM56 NOS DAC. I have the design finished at a high level, working out some details. This is a first for me, digital design, so hoping to gain some insight from those with technical / engineering experience.
Here it goes: when it comes to the power supply for single channel DAC chips, like PCM56, is it beneficial to use separate supplies for each channel?
For instance, PCM56 requires VS+ and VS- (analog), VL+ and VL- (logic). I plan to separate these four supplies - so four supplies minimum plus the digital supply. If I were to use separate supplies for each channel, or at the very least split each supply rail at some point for L and R, the DAC would have in total eight supplies (plus digital)! As you can imagine, this is a nightmare to lay out on a board...so would be interested to know if there is a benefit.
Let me know what you think, thanks
I am working on a parallel PCM56 NOS DAC. I have the design finished at a high level, working out some details. This is a first for me, digital design, so hoping to gain some insight from those with technical / engineering experience.
Here it goes: when it comes to the power supply for single channel DAC chips, like PCM56, is it beneficial to use separate supplies for each channel?
For instance, PCM56 requires VS+ and VS- (analog), VL+ and VL- (logic). I plan to separate these four supplies - so four supplies minimum plus the digital supply. If I were to use separate supplies for each channel, or at the very least split each supply rail at some point for L and R, the DAC would have in total eight supplies (plus digital)! As you can imagine, this is a nightmare to lay out on a board...so would be interested to know if there is a benefit.
Let me know what you think, thanks
Having separate power supplies allows more flexibility in how you route grounds. Running everything ultimately from a single power source means the ground routing becomes challenging because all GNDs are already connected together at the PSU and one thing you definitely want to avoid are ground loops.
I was considering this approach, I'll investigate, will have to look into the grounding implications, think I have a good idea of how it could be accomplished.
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If your design features multiple paralleled DAC chips for each channel, I suggest that you consider individually isolating/regulating all of those chips. I suggest that because, you would want the supplies to the paralleled DAC chips to be maximally isolated, so as to maximize their de-correlation. The de-correlation of noise and certain errors is the primary point of having DAC chips in parallel, which provides a net reduction of those undesired factors. This benefit is compromised should noise and errors be correlated though the power supply. In addition, such isolation inherently provides maximum channel separation as well.
If you would rather not go to such lengths, then there may not be a compelling reason to bother with paralleling in the first place.
Just my two cents worth.
If you would rather not go to such lengths, then there may not be a compelling reason to bother with paralleling in the first place.
Just my two cents worth.
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Physically, how would you achieve this? Using separate ground planes for each supply then combining at a star point? Or keep the grounds isolated and connecting each at a single one point to the larger ground plane? My understanding was the supplies would all be connected at one plane, keeping the impedance as low as possible on that plane. Thanks for your input.
Hi Ken - so it seems that taking what I had suggested a step further, you would even using separate supplies for the paralleled chips. I'll keep that in mind, certainly takes the complexity of the supply up a notch, but I end up using separate PCBs for R and L channels, it could be done...thanks.
I was thinking that the GNDs would only be all connected together via the ground plane. So each supply comes from a separate trafo winding.
Okay yes, that was my intention, all grounds on one large ground plane with dedicated layer, all supplies from separate traffo secondaries, may use a 4-layer PCB for this purpose with dedicated ground and power planes, then signal tracing on the other two.
I am going to look into rayma's idea to use separate PCBs for each channel and Ken's idea to run each chip from separate supplies as well. Will connect both channel PCB ground planes and digital ground planes at a single star point, likely by bus bar or copper braid to keep impedance / inductance low.
Every day this power supply becomes more complex! Hopefully though the extra complexity will yield better sound and measured performance.
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I think the question of whether each DAC chip should have its own separate supply comes down to the PSRR of the DAC chip. I'm designing multiple-parallel DACs and so far haven't noticed degradation from running up to six chips from a single TL431 which isn't known for its ultra-low noise. This is using TDA1387(*) which has no PSRR spec but I did make a measurement once and have forgotten what it was
There are two main advantages that I see for paralleling - one is to have more signal for the I/V stage and the other is to reduce the DAC's intrinsic noise through averaging.
(*) I should mention this is only a 16bit chip - if you're aiming for higher performance the PSRR becomes more critical by 6dB for each extra bit.
There are two main advantages that I see for paralleling - one is to have more signal for the I/V stage and the other is to reduce the DAC's intrinsic noise through averaging.
(*) I should mention this is only a 16bit chip - if you're aiming for higher performance the PSRR becomes more critical by 6dB for each extra bit.
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This was my thought too and the reason I asked the question - unfortunately, the PCM56 datasheet does not give any performance spec in terms of PSRR like I have seen on other datasheets. I would think if the PSRR were reasonably high, running multiple chips from a single supply would not be an audible problem.
My main motivation for using parallel chips is higher output signal for I/V stage. I am using all passive I/V with Sowter 1465 SUT. Taking this approach, output voltage vs. output impedance becomes a compromise - higher primary impedance for higher output voltage will increase the output impedance and vice versa. Paralleling two PCM56 helps with that issue, cutting the output impedance in half for the same voltage output. I was considering even more PCM56 in parallel, however I am using I2SoverUSB module from JLSounds. Lyuben at JLSounds tells me that running more than two PCM56 in parallel will require a buffer circuit between the module and PCM56, which is a design complexity I hope to avoid.
So, two PCM56 in parallel, maximizing output voltage with 1465 SUT balanced against an acceptable output impedance. I wish I knew the PSRR of the PCM56 so I could make a judgment on running the parallel chips from a single supply.
*Correction on the above - the PCM56 DOES provide a graphical representation of chip PSRR - around 54dB for the positive supplies, 78dB for the negative supplies.
Your thoughts abraxalito - high enough to run from the same supply? I think I may try it. Perhaps worth noting my supply is using two series regulators in cascade with roughly 120dB suppression at 120Hz and very low output impedance in simulation, max 0.2ohm at low frequencies.
Your thoughts abraxalito - high enough to run from the same supply? I think I may try it. Perhaps worth noting my supply is using two series regulators in cascade with roughly 120dB suppression at 120Hz and very low output impedance in simulation, max 0.2ohm at low frequencies.
So with the feedback above, here is what I am thinking.
-Running one pair of PCM56 in parallel per channel, +/- 2mA output current
-Will use dual mono PCB design - one signal PCB per channel
-Third separate PCB with digital supply for I2SoverUSB module
-All three boards will have low impedance common star ground point
Here is a draft of a single channel with pair of parallel PCM56. The two boards (R and L channel) will be stacked. Each board contains separate VS+, VS-, VL+, and VL- supplies that will be shared by parallel PCM56. Sowter 1465 SUT will be chassis mounted off to the right of the PCM56. Will adjust the secondary I/V resistor to find a balance between output voltage and output impedance.
-Running one pair of PCM56 in parallel per channel, +/- 2mA output current
-Will use dual mono PCB design - one signal PCB per channel
-Third separate PCB with digital supply for I2SoverUSB module
-All three boards will have low impedance common star ground point
Here is a draft of a single channel with pair of parallel PCM56. The two boards (R and L channel) will be stacked. Each board contains separate VS+, VS-, VL+, and VL- supplies that will be shared by parallel PCM56. Sowter 1465 SUT will be chassis mounted off to the right of the PCM56. Will adjust the secondary I/V resistor to find a balance between output voltage and output impedance.
I have a concern about using passive I/V with this particular chip. As far as I can tell the architecture is current-output R2R and such DACs are exquisitely sensitive to the voltage at the output node. Which is why they provide an on-chip opamp. The linearity will suffer significantly in passive I/V mode I fear.
As regards the complexity of a buffer circuit - a single SO14 HCMOS IC wouldn't be something to lose any sleep over. If you've got the chips don't let the need for a buffer dissuade you from using them.
As regards the PSRR plots - looks like you need to keep the supplies clean at HF (use large enough decouplers) otherwise I think you'll be fine.
Thanks for the input abraxalito - I had planned to use 1uF decoupler right at the PS pins per datasheet recommendations, if I experience issues I will experiment with other values. And duly noted on the HCMOS buffer, I will look into it.
As far as passive I/V, I did look into others experiences with this chip - it is current output R2R, others have seen good performance with passive resistor I/V as high as 500ohm, although more typical is 100ohm.
Given that I am using 1:10 SUT to provide voltage gain as opposed to an active gain stage, secondary resistor will likely be on the order of 2K to 5K, so reflected load to the Iout pin will be 20-50ohm, so I am hoping to see good linearity from the chip, but of course the transformer will provide its own nonlinearities.
We will see! I'll report back here with the results when I have them, probably a month at least.
As far as passive I/V, I did look into others experiences with this chip - it is current output R2R, others have seen good performance with passive resistor I/V as high as 500ohm, although more typical is 100ohm.
Given that I am using 1:10 SUT to provide voltage gain as opposed to an active gain stage, secondary resistor will likely be on the order of 2K to 5K, so reflected load to the Iout pin will be 20-50ohm, so I am hoping to see good linearity from the chip, but of course the transformer will provide its own nonlinearities.
We will see! I'll report back here with the results when I have them, probably a month at least.
Did the others you saw share any measurements with passive I/V? I'm curious if the high level THD degrades as much as theory would suggest. Or perhaps the designers have a proprietary trick which keeps the distortion under control even with significant excursions at the output pin?
If its really Iout R2R with no proprietary tricks then I'd expect DAC distortion to exceed trafo distortion from the mid-range and up at moderate output levels.
Just a FYI - here (on the right, ignore the left plot its a distraction) is a measurement of a multibit R2R Iout DAC where (I suspect) the opamp doesn't have a low enough offset voltage. This isn't passive I/V this is opamp I/V with a non-zero voltage at the DAC output. Probably of the order of a mV or so. Imagine what happens with tens of mV.
Review: Battle of Schiit Audio DACs | Page 2 | Audio Science Review (ASR) Forum
If its really Iout R2R with no proprietary tricks then I'd expect DAC distortion to exceed trafo distortion from the mid-range and up at moderate output levels.
Just a FYI - here (on the right, ignore the left plot its a distraction) is a measurement of a multibit R2R Iout DAC where (I suspect) the opamp doesn't have a low enough offset voltage. This isn't passive I/V this is opamp I/V with a non-zero voltage at the DAC output. Probably of the order of a mV or so. Imagine what happens with tens of mV.
Review: Battle of Schiit Audio DACs | Page 2 | Audio Science Review (ASR) Forum
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I haven't come across plots, but diyAudio user Bernhard claims no harmonics above -90dB with 1kHz tone at 0dB with 500ohm passive I/V here.
Building the ultimate NOS DAC using TDA1541A
Vague on the details, so I will take my own measurements of course
Building the ultimate NOS DAC using TDA1541A
Vague on the details, so I will take my own measurements of course