That's a real problem indeed when DC coupling and high input resistance is wanted.
I solve this by cascoding it (Vds fixed at about 2V). That makes the gate leakage almost non-existant and the buffer's sonics improves significantly.
You can easily trim DC offset by using a higher Idss JFET at the negative rail and vary the source resistor of that JFET.
Patrick
Patrick
You only need close Idss. +-0.5% is ideal, +-5% is just about OK. You can still use source resistor for fine trimming.
You need 2pairs for a stereo build.
I would expect you can get that from 10ff. Maybe from fewer.
You need 2pairs for a stereo build.
I would expect you can get that from 10ff. Maybe from fewer.
I guess using two Bf862 will reduce output impedence and may be better power handling( heat dissipation)? Keeping everything else same?
The heat disspation will only go down if you reduce Id and/or Vds.
Using two in parallel does not reduce power dissipation.
Using two in parallel does not reduce power dissipation.
So just the output impedence then, what would be reasonable number for Output impedence . Original B1 is close to 33 from Patrick's post.
Here is a schematic. It has three JFETs all in parallel. Q101 &Q100 are K117,the other two are smd BF862,I will try both parallel and single configuration.
Thanks to Juma ,Andrew ,EUVL and Nelson. I incorporated all your ideas.
Hope I have not screwed up anything.
Please take a look.😀
Thanks to Juma ,Andrew ,EUVL and Nelson. I incorporated all your ideas.
Hope I have not screwed up anything.
Please take a look.😀
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Hi Patrick, not much experience here, but at least I can say that my B1 runs very well on BF862's (without gate stopper resistors for now) - sounds awesome.
Here is my humble build: http://www.diyaudio.com/forums/pass-labs/124889-b1-buffer-preamp-421.html#post5011120
This thread started off very well and there is some valuable info here, unfortunately most of the technicalities I still do not understand (yet).
Jerry
PCBs
here is the PCb. Please let me know if there are any design flaws.
So the board has option to use one or two BF862 or an 2SK170.Also play with and without gate resistors for current source jfets.
here is the PCb. Please let me know if there are any design flaws.
So the board has option to use one or two BF862 or an 2SK170.Also play with and without gate resistors for current source jfets.
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I am still waiting after 4 weeks for pcbs to arrive.I ordered components yesterday.
so this is the plan I understand from here.
Getting 30 BF862 and will look for 2(4 for parallel) close matched idss pairs(<5%Difference in IDSS).
Using a combination of trimmer(200ohm) and a fixed resistor to set Id less than Idss.And this combination will be used in both upper and lower source resistors to maintain Id lower than Idss?
Still not sure if I need a gate resistor at the gate of courrent source JFET?I will use a 400ohm as gate resistor for signal jfet.
everything else same as original design.
Please let me know if this sounds ok or not.
so this is the plan I understand from here.
Getting 30 BF862 and will look for 2(4 for parallel) close matched idss pairs(<5%Difference in IDSS).
Using a combination of trimmer(200ohm) and a fixed resistor to set Id less than Idss.And this combination will be used in both upper and lower source resistors to maintain Id lower than Idss?
Still not sure if I need a gate resistor at the gate of courrent source JFET?I will use a 400ohm as gate resistor for signal jfet.
everything else same as original design.
Please let me know if this sounds ok or not.
Earno Borbely article on parallel Jfets
http://www.audioxpress.com/assets/upload/files/Erno BorbelyJFETs The New Frontier Part 1and 2.pdf
http://www.audioxpress.com/assets/upload/files/Erno BorbelyJFETs The New Frontier Part 1and 2.pdf
With its noise density at 0.8nV/sqHz, paralleling 3 pairs will bring ~0.5nV/sqHz and almost no noise current. Looks nice!
Wish I know how to design a circuit with 3.But then how many JFEts one need to buy to get a iDs c match?
Paralleled jFETs have been recommened and used for the inputs of very low source voltages. Many Members have implemented this and I can't recall any coming back to say the non matching ruined the performance of the stage. I do recall a few coming back and reporting that matching was unimportant.
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