Hello everyone.
Since I always loved my stereo ESP P3A amp, I built an "upgraded" version of it. I made PCB for the two amps.
The schematic is attached. As you can see, I ugraded input transistors with 2SC1775s (high hfe, low noise), VAS transistor with a 2SA1406 (very low Cob), and got faster driver transistors (2SB649, 2SD669). I kept MJLs as output transistors as I got some samples from Onsemi for free.
I increased the capacitance of NFB and bootstrap caps (330uF instead of 100uF); I used Black Gates here. They aren't in the schematic but I also included 220uF bypass caps for the supply rails (Elna RJH, low ESR, equivalent to Pana FC). These are placed near output transistors; close to the input stage I bypassed the supply rails with two Wima MKP4 0.1uF caps.
All resistors are Holco H4.
I reduced C4 (Miller cap) to 68pF and provided feedforward compensation with a 10pF cap between VAS collector and negative LTP input.
I don't have a square wave generator. However, if I feed a sine wave into the amp, I have a small oscillation in the negative half of the wave. It starts when the signal approaches the negative peak, and it ceases when the signal crosses zero again. The positive half is clean. This happens for output signals greater than 4-5 Vpp, and only when the speaker is connected. With no speaker, the output is clean.
First thing I did was to remove feedforward compensation. Nothing changed. Then I tried to increase the miller cap. The ringing somewhat decreases but it is essentially the same for 82, 100 and 120 pF Miller caps. The oscillation is absolutely identical for the two amps.
So I tried to fit a 0.1uF cap across the two driver transistor bases. But now, while one amp is completely clean (also with 68pF miller and 10pF FF comp caps), in the other I have a strange peak (with noise) during the descending front of the negative half of the sine wave, starting from 3.5/4 kHz.
This is very strange to me, since the amps perform perfectly identical (oscillation and sound; most parts are matched) without this cap.
Any advice?
Thank you!
Since I always loved my stereo ESP P3A amp, I built an "upgraded" version of it. I made PCB for the two amps.
The schematic is attached. As you can see, I ugraded input transistors with 2SC1775s (high hfe, low noise), VAS transistor with a 2SA1406 (very low Cob), and got faster driver transistors (2SB649, 2SD669). I kept MJLs as output transistors as I got some samples from Onsemi for free.
I increased the capacitance of NFB and bootstrap caps (330uF instead of 100uF); I used Black Gates here. They aren't in the schematic but I also included 220uF bypass caps for the supply rails (Elna RJH, low ESR, equivalent to Pana FC). These are placed near output transistors; close to the input stage I bypassed the supply rails with two Wima MKP4 0.1uF caps.
All resistors are Holco H4.
I reduced C4 (Miller cap) to 68pF and provided feedforward compensation with a 10pF cap between VAS collector and negative LTP input.
I don't have a square wave generator. However, if I feed a sine wave into the amp, I have a small oscillation in the negative half of the wave. It starts when the signal approaches the negative peak, and it ceases when the signal crosses zero again. The positive half is clean. This happens for output signals greater than 4-5 Vpp, and only when the speaker is connected. With no speaker, the output is clean.
First thing I did was to remove feedforward compensation. Nothing changed. Then I tried to increase the miller cap. The ringing somewhat decreases but it is essentially the same for 82, 100 and 120 pF Miller caps. The oscillation is absolutely identical for the two amps.
So I tried to fit a 0.1uF cap across the two driver transistor bases. But now, while one amp is completely clean (also with 68pF miller and 10pF FF comp caps), in the other I have a strange peak (with noise) during the descending front of the negative half of the sine wave, starting from 3.5/4 kHz.
This is very strange to me, since the amps perform perfectly identical (oscillation and sound; most parts are matched) without this cap.
Any advice?
Thank you!
An externally hosted image should be here but it was not working when we last tested it.
IMO the CFP output stage is a nightmare....
You might find that you need some Miller capacitance on Q6
You might find that you need some Miller capacitance on Q6
Try to put a LR filter at the output , 1uH in paralel
with a 1R/3W non inductive resistor...
You can also reduce the transconductance of the differential
pair using two 47R or 100R resistors in serial with the
emitters of the 2SC1775. (Q1 and Q2)
This should tame down the oscillations...
with a 1R/3W non inductive resistor...
You can also reduce the transconductance of the differential
pair using two 47R or 100R resistors in serial with the
emitters of the 2SC1775. (Q1 and Q2)
This should tame down the oscillations...
This reduces in both cases the Miller-capacitance, so you have a lot less phase/gain margin - means asking for stability problems.
If you don't have gear to test stability (especially into capacitive loads) I would go back to original values. Stick with the new transistor and increase C4 to the original value + the difference in Cob between original and new transistor.
Have fun, Hannes
10Pf cap doesnt show on the schematic ...also there is supposed to be a miller cap also nad the negative driver as other forum memebers indicated ...
usefull will be to have a picture of your pcb often things like that can be pcb related
usefull will be to have a picture of your pcb often things like that can be pcb related
10pF can easily be pcb-related.
Reducing Miller-capacitance by using even lower Cob transistors and in addition a lower Miller-cap is asking for troubles. The orignal values were there for a reason.
Have fun, Hannes
Agree with Hannes. You should not reduce the miller cap in this design. Further, the 100pF from C to B on Q6 is vital - this is, after all, the very side the instability occurs.
IMHO, a CFP is not well suited to Class AB. Class A - an entirely different matter.
I would suggest you try the Self EF Type II output stage, more stable, though less exotic. Then you should be able to actually reduce the miller cap, not before.
Hope this is helpful,
Hugh
IMHO, a CFP is not well suited to Class AB. Class A - an entirely different matter.
I would suggest you try the Self EF Type II output stage, more stable, though less exotic. Then you should be able to actually reduce the miller cap, not before.
Hope this is helpful,
Hugh
here are some updates:
I eliminated the feedforward compensation and increased the VAS miller cap to 220pF. The oscillation is still there.
With the original value for the miller cap (100pF) I tried to fit a 100pF across B and C of Q6. The oscillation was still there, and maybe was a little worse than without it.
I have no clue. Attached is the PCB layout.
I eliminated the feedforward compensation and increased the VAS miller cap to 220pF. The oscillation is still there.
With the original value for the miller cap (100pF) I tried to fit a 100pF across B and C of Q6. The oscillation was still there, and maybe was a little worse than without it.
I have no clue. Attached is the PCB layout.
Attachments
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to my opinion with this design of pcb you simply have no chance ..... traces down under C7 and C 3 are simply out of the question
also keep in mind that often electrolytics at this size in the signal path turn microphonic resulting to may unwanted situations
have you ever heard the term star ground ??? also current source at this distance will never work well ( needs to be as close is possible to the ltp )
also keep in mind that often electrolytics at this size in the signal path turn microphonic resulting to may unwanted situations
have you ever heard the term star ground ??? also current source at this distance will never work well ( needs to be as close is possible to the ltp )
If you have oscillation occuring only on the negative half of the waveform as it approaches or leaves the peak value, then it seems to me you have an output stage stability problem here. But, to verify this, you should take a look at what frequncy this is happening at - typically it will be above 1MHz. Overall loop stability problems are GENERALLY in the 100's of KHz range.
I have to agree with all the comments and advice passed above:-
1. Stick to the original design values
2. It is a mistake to think that by reducing Cdom you get a faster, lower distortion amplifer (if you do a sim in spice, as you lower Cdom you do get a wider bandwidth, lower HF distortion and faster slew rate . . . don't be fooled - what you will end up with is a marginally stable amplifier prone to oscillation. Slew rate, distortion, bandwidth and stability is a tradeoff game.
3. Good recomndation to apply some degeneration to the LTP
4. This amp has a CFP output stage - as already noted, layout is critical. This type of stage is prone to instability and you really need to know what you are doing to use it successfully. Comment regarding problems when used in class B or AB are spot in in my view - better to go for an emmiter follower - Self type II or III
Good luck
I have to agree with all the comments and advice passed above:-
1. Stick to the original design values
2. It is a mistake to think that by reducing Cdom you get a faster, lower distortion amplifer (if you do a sim in spice, as you lower Cdom you do get a wider bandwidth, lower HF distortion and faster slew rate . . . don't be fooled - what you will end up with is a marginally stable amplifier prone to oscillation. Slew rate, distortion, bandwidth and stability is a tradeoff game.
3. Good recomndation to apply some degeneration to the LTP
4. This amp has a CFP output stage - as already noted, layout is critical. This type of stage is prone to instability and you really need to know what you are doing to use it successfully. Comment regarding problems when used in class B or AB are spot in in my view - better to go for an emmiter follower - Self type II or III
Good luck
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I am very convinced the oscillation takes place in the output stage because:
-it takes place only in the negative half of the wave;
-The frequency is in the MHz area;
-Basically it is not dependant on the VAS miller capacitance value: I have oscillation with Cdom as high as 220pF, and it doesn't increase until I go down to 47pF or less (but then the oscillation looks different);
-without speaker, the output is clean.
A 100nF cap across driver transistor bases helped, but then in one channel I had strange peaks in the waveform (always in the negative half)
What is strange to me, is that a 100pF cap between B and C of the negative driver transistor seemed to worsen things.
One possible solution might be to redraw the board for an EF output stage. I'll think about that, but I am reluctant to accept this oscillation is not fixable.
-it takes place only in the negative half of the wave;
-The frequency is in the MHz area;
-Basically it is not dependant on the VAS miller capacitance value: I have oscillation with Cdom as high as 220pF, and it doesn't increase until I go down to 47pF or less (but then the oscillation looks different);
-without speaker, the output is clean.
A 100nF cap across driver transistor bases helped, but then in one channel I had strange peaks in the waveform (always in the negative half)
What is strange to me, is that a 100pF cap between B and C of the negative driver transistor seemed to worsen things.
One possible solution might be to redraw the board for an EF output stage. I'll think about that, but I am reluctant to accept this oscillation is not fixable.
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This is then very likely output stage stability - CFP output stages are very tricky. I'd go with an EF type II as advised earlier in this thread. Redraw your circuit and post it up and the forum members will help you with your design so you get it right first time.
it is your choise to take a working circuit and mess arround with it .... 100 nf across your outputs and all your sonics are seriously gone .... probably together with your band width
as i said once more you cannot treat electronics with kortizone ...meaning there is no point to try to suppress the problem ....you have to kill it where it starts ....
if your problem lays in the vas for example then the output stage is simply going to amplify it....
as i said once more you cannot treat electronics with kortizone ...meaning there is no point to try to suppress the problem ....you have to kill it where it starts ....
if your problem lays in the vas for example then the output stage is simply going to amplify it....
Try 100 R resistors in series with the bases of Q5 and Q6.You might
want to play with the value of these resistors in the range of 47R to 470R.
Hope this helps.It has helped me a few times with CFP outputs.
Best Regards
Selim
want to play with the value of these resistors in the range of 47R to 470R.
Hope this helps.It has helped me a few times with CFP outputs.
Best Regards
Selim
CFPs are extremely tetchy in Class AB. Fine in Class A, but marginal in Class AB.
100R base stoppers on the drivers and 10R base stoppers on the outputs will improve things just as Selim has observed.
The Type II EF NEVER does this if base stoppers are used. In my experience even well controlled the CFP does not sound any better. People use it because it is excruciatingly elegant. But it's also tetchy to bias, and is best used only single ended Class A IMHO.
Your input and VAS stages are fine.
Hugh
100R base stoppers on the drivers and 10R base stoppers on the outputs will improve things just as Selim has observed.
The Type II EF NEVER does this if base stoppers are used. In my experience even well controlled the CFP does not sound any better. People use it because it is excruciatingly elegant. But it's also tetchy to bias, and is best used only single ended Class A IMHO.
Your input and VAS stages are fine.
Hugh
Thats becasue the upper driver is just a buffer and the bottom driver is inverting and has gain. To keep upper and lower gains the same gain requires a 220pf from BC on Q6.
Had exact same problem with my quasi design.
Thank you all for your help.
Hugh, just like you, I think my input and VAS stage are indeed fine. I think this is confirmed by the fact that changing Cdom in the VAS stage from 68 to 220pF doesn't change the oscillation.
As written by someone, and also by Self in his book, "one half" oscillation indicates OP stage instability, to which CFP topology is particularly prone.
Slone writes that 3281/1302 OP transistors (of which I consider my MJL4281/4302 their successors) are particularly unfortunate to be used in a CFP topology, unless low capacitance drivers are used. I use 2SB649/2SD649, which have good Cob (25-30pF), but not extremely low. I have read elsewhere on this boards that in my particular configuration this value of drivers Cob may be too high.
The fact that a 100pF cap across B and C of the negative driver worsen slightly things, seems to confirm this.
So I think that one last thing to do before redrawing the board with an EF OPS would be trying drivers with extremely low Cob. Tomorrow I'll go get some 2SA1209/2SC2911; their Cob is 3-4 pF. Their power/current ratings are less conservative, but I'm curious if this reduces the oscillation.
If I understand well, the dangerous thing in my configuration is having drivers not too faster than output transistors (that are very fast) in a close feedback loop. Their poles are not enough spaced and I have excessive phase shift in the MHz range. A much faster driver should have its pole farther from the one of the output transistor.
I'll try this and let you know!
PS. Trying slower OP transistors would be another idea, I just thought of the drivers first because I think they'll be cheaper for a try. However, MJL21193/4 come to mind, do you have other ideas?
Hugh, just like you, I think my input and VAS stage are indeed fine. I think this is confirmed by the fact that changing Cdom in the VAS stage from 68 to 220pF doesn't change the oscillation.
As written by someone, and also by Self in his book, "one half" oscillation indicates OP stage instability, to which CFP topology is particularly prone.
Slone writes that 3281/1302 OP transistors (of which I consider my MJL4281/4302 their successors) are particularly unfortunate to be used in a CFP topology, unless low capacitance drivers are used. I use 2SB649/2SD649, which have good Cob (25-30pF), but not extremely low. I have read elsewhere on this boards that in my particular configuration this value of drivers Cob may be too high.
The fact that a 100pF cap across B and C of the negative driver worsen slightly things, seems to confirm this.
So I think that one last thing to do before redrawing the board with an EF OPS would be trying drivers with extremely low Cob. Tomorrow I'll go get some 2SA1209/2SC2911; their Cob is 3-4 pF. Their power/current ratings are less conservative, but I'm curious if this reduces the oscillation.
If I understand well, the dangerous thing in my configuration is having drivers not too faster than output transistors (that are very fast) in a close feedback loop. Their poles are not enough spaced and I have excessive phase shift in the MHz range. A much faster driver should have its pole farther from the one of the output transistor.
I'll try this and let you know!
PS. Trying slower OP transistors would be another idea, I just thought of the drivers first because I think they'll be cheaper for a try. However, MJL21193/4 come to mind, do you have other ideas?
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Hi Christian,
As a rule, and confining my comments to the CFP output stage, I've found in Class A applications (where I often use CFP) that the drivers should be no more than three times faster (as indicated by Ft) than the outputs for best stability. Similar speeds are good, in fact. A good combination is MJE15030/31 and MJL21193/94. The 3281s you have chosen are 30MHz devices, quite fast, and I suggest a slower device (with arguably lower transconductance, too, as the output device largely determines the loop gain).
Nigel, I cannot see that the two drivers of a CFP output stage, one npn and the other pnp, are in different topologies. Both are driven at their bases by a common voltage source- the collector of the VAS - and both have their emitters to the load and collectors to the output device bases. They are both CFPs, simply complementary. In the case of an npn quasi, the upper driver and output are a darlington, while the lower is indeed a CFP, just as you say - they are different here (and sound damn good). In this instance there should be some artifice on the emitter of the lower, pnp driver to simulate the large base-emitter junction of the upper darlington, though the capacitor, typically 22nF, is generally across the diode used for this purpose. JLH has much to say on this one.
Given the fact that there are two phase reversals within a CFP, driver input to output, and again output device base to collector, we have, with two very different dies, a nasty pole with lots of phase shift. I would contend that the DEF Type II is FAR more stable, and that this is a most desirable quality BECAUSE we are driving a highly reactive load - both electrically, and electrodynamically - a speaker. While the CFP is unarguably elegant, it has this very serious phase shift issue which makes it far less than ideal with reactive loads. For this task, we need a high duty emitter follower.....
Hope this is helpful, and propels you towards the best implementation,
Hugh
As a rule, and confining my comments to the CFP output stage, I've found in Class A applications (where I often use CFP) that the drivers should be no more than three times faster (as indicated by Ft) than the outputs for best stability. Similar speeds are good, in fact. A good combination is MJE15030/31 and MJL21193/94. The 3281s you have chosen are 30MHz devices, quite fast, and I suggest a slower device (with arguably lower transconductance, too, as the output device largely determines the loop gain).
Nigel, I cannot see that the two drivers of a CFP output stage, one npn and the other pnp, are in different topologies. Both are driven at their bases by a common voltage source- the collector of the VAS - and both have their emitters to the load and collectors to the output device bases. They are both CFPs, simply complementary. In the case of an npn quasi, the upper driver and output are a darlington, while the lower is indeed a CFP, just as you say - they are different here (and sound damn good). In this instance there should be some artifice on the emitter of the lower, pnp driver to simulate the large base-emitter junction of the upper darlington, though the capacitor, typically 22nF, is generally across the diode used for this purpose. JLH has much to say on this one.
Given the fact that there are two phase reversals within a CFP, driver input to output, and again output device base to collector, we have, with two very different dies, a nasty pole with lots of phase shift. I would contend that the DEF Type II is FAR more stable, and that this is a most desirable quality BECAUSE we are driving a highly reactive load - both electrically, and electrodynamically - a speaker. While the CFP is unarguably elegant, it has this very serious phase shift issue which makes it far less than ideal with reactive loads. For this task, we need a high duty emitter follower.....
Hope this is helpful, and propels you towards the best implementation,
Hugh
I did some more experimenting.
As suggested by Hugh, I tried drivers with similar speed as the output transistors (MJL4281/4302). I had MJE15034/5 available so I tried those. Their fT is 30MHz, against 35 of the output transistors.
The oscillation worsened sensibly: on the bottom half peak it almost doubled at 2-3 W on my 8 ohm speaker.
Then I tried some very low Cob drivers: 2SA1209/C2911. The oscillation almost disappeared. There are still traces of it. However @ 2-3W output, if I increase the quiescent current up to 200mA, the oscillation disappears completely.
Seen the oscillation decrease with faster drivers, last try I will do is with slower output transistors. I just ordered some samples of MJL21193/4.
I will let you know. Thanks again for all the advice.
PS. When I have some time I'll try and build a version of this amp with an EF output stage, and see how I like its sound.
As suggested by Hugh, I tried drivers with similar speed as the output transistors (MJL4281/4302). I had MJE15034/5 available so I tried those. Their fT is 30MHz, against 35 of the output transistors.
The oscillation worsened sensibly: on the bottom half peak it almost doubled at 2-3 W on my 8 ohm speaker.
Then I tried some very low Cob drivers: 2SA1209/C2911. The oscillation almost disappeared. There are still traces of it. However @ 2-3W output, if I increase the quiescent current up to 200mA, the oscillation disappears completely.
Seen the oscillation decrease with faster drivers, last try I will do is with slower output transistors. I just ordered some samples of MJL21193/4.
I will let you know. Thanks again for all the advice.
PS. When I have some time I'll try and build a version of this amp with an EF output stage, and see how I like its sound.
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