Try looking for my posts on capacitance distribution, self-screening and series vs parallel secondary windings.
An OPT doesn't like series secondary windings with different primary to secondary capacitance values.
P.S. You also slightly deviate from the optimum leakage inductance interleaving rule.
An OPT doesn't like series secondary windings with different primary to secondary capacitance values.
P.S. You also slightly deviate from the optimum leakage inductance interleaving rule.
You want the outer packages to be 1/2 turns of the internal packages. For example, P3-S-P6-S-P6-S-P3. P3s are 1/2 of P6. However, this criteria is not a top priority.
I also found the optimal arrangement by experimenting:
https://www.diyaudio.com/community/...without-global-nfb.384100/page-4#post-6987619
https://www.diyaudio.com/community/...without-global-nfb.384100/page-5#post-6991884
https://www.diyaudio.com/community/...without-global-nfb.384100/page-4#post-6987619
https://www.diyaudio.com/community/...without-global-nfb.384100/page-5#post-6991884
Thank you so much, that's an interesting design.
There is one thing though; I've read somewhere many years ago that Anode tap should be close to the bobbin because MLT is less there and so inter-winding capacitance.
To shoot that dip resonance high and lowest Q, you need to:
1. Reduce P/S capacitance the most at high potential regions, by epsilon, dielectric thickness or redirecting that capacitance into the primary, dump it.
2. Shunt all secondary layers to the same potential. Either by paralleling windings, or use screens if series connected secondary windings are needed. For some cases, especially OPTs, parallel/series combo of correct/critical layers works well.
3. Always remember that different p/s capacitance values within the coil gives capacitive bridging between layers, if these layers are far away, high Ls, high turn count, then this capacitance bridge is asking for trouble. Imagine it like connecting different transformers via capacitors. The more interleaves you got, the higher the "transformer" count, all differently valued RLC networks. By playing with capacitance distribution for a while, you can learn to make them interact less. Parallel connected secondaries do that. I call it "auto-screening".
1. Reduce P/S capacitance the most at high potential regions, by epsilon, dielectric thickness or redirecting that capacitance into the primary, dump it.
2. Shunt all secondary layers to the same potential. Either by paralleling windings, or use screens if series connected secondary windings are needed. For some cases, especially OPTs, parallel/series combo of correct/critical layers works well.
3. Always remember that different p/s capacitance values within the coil gives capacitive bridging between layers, if these layers are far away, high Ls, high turn count, then this capacitance bridge is asking for trouble. Imagine it like connecting different transformers via capacitors. The more interleaves you got, the higher the "transformer" count, all differently valued RLC networks. By playing with capacitance distribution for a while, you can learn to make them interact less. Parallel connected secondaries do that. I call it "auto-screening".
Thank you so much, I'm reading all your previous posts and I'm learning a lot. BTW I can't quite understand this one, can you explain it a little more?
Thanks again
Sajad
This is excellent data that I would love to be able to do myself.
I am not however 100% clear on your test setup.
Honestly I believe your test setup deserves it own thread and I think members like myself would benefit from the learning.
Measuring transformers and coming up with good data is a poorly understood area for many including myself.
If you can find the time it would be great to see a thread on the measurement methods you used here.
Thank you, Actually I'm learning right now and it seems I know nothing about OPTs myself! 50AE has some excellent posts about designing and testing transformers which I wish I was aware of them before, but you are right; testing OPTs is as important as building them and I gathered some information about it and also build a jig for it. I will build a new thread and post everything I know about testing ASAP.
Question.
Does the numbers tell the turns ratio from the secondary?
Or are the numbers the impedance ration from the secondary?
I can not quite make sense of the numbers to get your target 2.5K:8ohm impedance ratio
2500primare /8 secondary = 312.5 impedance ratio or 312.5^.5 = 17.68 turns ratio
Or
Is the number the number of layers deep of wire in the section?
If the number is the number of wires deep in a section then is the coil being perfect wound?
When winding at home I never found how to keep a coil after a few layers deep perfect wound. They always ended up jumble wound after a few layers.
In my work years ago I designed special tooling and used a commercial coil winder to get prefect wound coils but not at home by hand.
What sort of winding setup do you use to make your coils? Lots to know here.
This tells the number of layers in each section of winding, meaning that the winding consists of 4 secondary section an 3 primary sections, and 6P means a section made of 6 layers of primary wire.
Every primary layer is made of 150 turns of 0.4mm wire making total number of 3000 primary turns, and every secondary section is actually made from two layers of 84 turns of .75 mm wire in series making total 168 turns of secondary and all secondary sections are in parallel to each other.
I use margins, meaning that 1 mm at the end of the bobbin at each side is not wire wound. I use an ID card as a measuring guage for this purpose.
I use a CNC winding machine built by myself. It's made of two stepper motors and an Arduino, here is the video: Link
Beautiful machine.
Not fast like commercial machines but very beautiful design and construction.
I can see the ladder I will have to climb is very long to wind high quality output transformers.
Not fast like commercial machines but very beautiful design and construction.
I can see the ladder I will have to climb is very long to wind high quality output transformers.
If you do not know how to calculate P/S capacitance, check Patrick Turner's papers, he explains it quite simply. I'll try to do so as well.
Let's take this interleaving configuration for example: P3-S-P6-S-P6-S-P3. Let's break this down more detailed and consecutive.
18 primary layers
3 secondary layers.
To calculate capacitance factor, we begin by labeling down each primary layer with the highest number at the highest alternating potential (voltage swing), this is where the anode is. So the anode layer is labeled as 18, like the maximum primary count, and the B+ layer labeled as 1. Remember the B+ layer is basically AC grounded, almost little to no voltage swing occurs there, for most cases we can consider negligible capacitance there.
B+---------P1---------r
q-----------P2---------r
q-----------P3--------p
//////////////////////////
------------S1----------
//////////////////////////
o-----------P4--------p
o-----------P5--------m
l------------P6--------m
l------------P7--------k
j------------P8--------k
j------------P9--------i
//////////////////////////
------------S1----------
//////////////////////////
h-----------P10--------i
h-----------P11-------g
f------------P12-------g
f------------P13-------e
d-----------P14-------e
d-----------P15-------c
//////////////////////////
------------S1----------
//////////////////////////
b-----------P16-------c
b-----------P17-------a
Anode-----P18-------a
To calculate P/S capacitance, which is the most dominant one within a traditional OPT, you assume the secondary layer is at ground potential, then you take each primary layer number at the interface and substract 0,5 from it to assume a midpoint. You have 6 P/S interfaces: P16, P15, P10, P9, P4, P3.
With midpoints, they become P15,5 ; P14,5 ; P9,5 ; P8,5 ; P3,5 : P2,5
Capacitance factors are calculated as follows: The max primary layer count, which is 18, becomes the denominator.
Cf1 = (P15,5/18)^2 = 0,74
Cf2 = (P14,5/18)^2 = 0,69
Cf3 = (P9,5/18)^2 = 0,28
Cf4 = (P8,5/18)^2 = 0,22
Cf5 = (P3,5/18)^2 = 0,04
Cf6 = (P2,5/18)^2 = 0,02
To calculate effective capacitance, multiply each factor by the static capacitance, which is the result of each individual surface area, dielectric constant and thickness. You can observe that capacitance is exponentially getting lower, with the same rate as impedance does, when progressing towards B+ windings.
So, how about that shielding and capacitance shunt. When the secondaries are all parallel, basically, all the capacitance gets dumped into a single region. When secondaries are connected in series, that capacitive difference between P/S interfaces makes it look like connecting two transformers in series. Hence distant primary layers are now capacitively crosstalking with each other and this worsens the dip resonance, because additional primary to primary leakage inductance kicks in.
Two strategies I'm using is the capacitance dump, that is redirecting high anode potential to the primary the most as possible. This shift the dip resonance more into peak resonance. The second strategy is making sure no "capacitive wandering" by series connected windings occur. However, the toolbox of options can be diverse and detailed elaboration is needed for each one.
For example, shunting two series connected secondaries by a single paralleled secondary also helps to a big extent. For example, if you have one 4R winding and two 1R windings, you can get a good performance by connecting two 1Rs in series, then paralleling this package to the 4R. The later keeps resonance behavior in shape.
Wow! That's a great answer, thanks alot! You really need to write a book on OPT because this knowledge is somehow going to disappear soon.
One question though; Is it important which side of secondary be connected to ground? I mean if secondaries are in series, should the side which is closer to plate side of primary be grounded or the other side?
Thanks again
Sajad
I've experimented some years ago. In some cases it might bring a little benefit, but the most detrimental factor remains the series connection of secondaries.
This doesn't mean of course, that one cannot get good performance with series secondary connections, but has to respect some rules. For example, this is not a problem with balanced push-pull transformers wound on two coils, where the P/S capacitances between both layers are equal. This brings no crosstalk between the primary layers, on the terms that the secondary ground point is also a mid one, not on one end. PP transformers, if correctly built, are easier in terms of parasitics.
To get good insight on advanced transformer design, one needs to elaborate each specific scenario with its unique interleaving schematic and application carefully. Rules on different transformers are not universal, different toolbox techniques apply for SE, PP OPTs, step-up, step down, unity interstage transformers, etc. OPTs for example are more forgiving towards capacitance distribution mistakes, whereas with interstage transformers, it is easy to screw up.
This doesn't mean of course, that one cannot get good performance with series secondary connections, but has to respect some rules. For example, this is not a problem with balanced push-pull transformers wound on two coils, where the P/S capacitances between both layers are equal. This brings no crosstalk between the primary layers, on the terms that the secondary ground point is also a mid one, not on one end. PP transformers, if correctly built, are easier in terms of parasitics.
To get good insight on advanced transformer design, one needs to elaborate each specific scenario with its unique interleaving schematic and application carefully. Rules on different transformers are not universal, different toolbox techniques apply for SE, PP OPTs, step-up, step down, unity interstage transformers, etc. OPTs for example are more forgiving towards capacitance distribution mistakes, whereas with interstage transformers, it is easy to screw up.
Excuse me if I am asking too many dumb questions; this means in high potential points like anode tap, the nearby windings should be primary layers not secondary, Am I correct? So for example, a winding arrangement like P-S-P-S-P which outer layers are primary should have less C compared to S-P-S-P-S , right?
Also that peak resonance that you mentioned is the result of parallel combination of Cp-p and Ls?
Also can you give me an example of how can this be done?
1. Yes, a P-S-P-S-P will have less Cps capacitance, compared to a S-P-S-P-S settings. However, both settings can be optimized and the S-P-S-P-S setting can be made no worse than the first counterpart by redirecting the primary layers.
2. The peak resonance is primarily the result of primary to primary capacitance together with Ls. However, some Cps capacitance can be transformed to Cpp capacitance, especially with parallel secondaries.
3. Shielding the secondaries to be connected in series with electrostatic screens that are constantly in parallel.
For example, P3-screen-S-screen-P6-screen-S-screen-P3. Connect the screens in parallel, no need to connect them to ground, usually float setting is enough.
You can also do that with triple secondary layers. For example, in the interleaving setting of P3-SSS-P6-SSS-P3, by sandwiching the mid secondaries between the outer secondaries and guaranteeing constant paralleling of the outer secondaries, you basically "protect" the mid secondaries and then you can series connect them without trouble.
A cheat around options works quite good with the S-P-S-P-S setting. Make the outer S windings 1/2 of the internal ones, for example 1R, and the inner winding 4R. That respect the leakage inductance rule. Then connect the 1R windings in parallel, let them stay that way. It is better to have distant secondary layers in parallel. Then you can connect the 1R package with the 4R in series for a 9R output impedance.
A simple rule of thumb that worked for me the most of the time is to parallel secondaries with a big physical distance and also large Cps difference.
If you have to connect two secondaries in series, paralleling them to an already parallel package (impedances need to be equal of course) also helps big time.
2. The peak resonance is primarily the result of primary to primary capacitance together with Ls. However, some Cps capacitance can be transformed to Cpp capacitance, especially with parallel secondaries.
3. Shielding the secondaries to be connected in series with electrostatic screens that are constantly in parallel.
For example, P3-screen-S-screen-P6-screen-S-screen-P3. Connect the screens in parallel, no need to connect them to ground, usually float setting is enough.
You can also do that with triple secondary layers. For example, in the interleaving setting of P3-SSS-P6-SSS-P3, by sandwiching the mid secondaries between the outer secondaries and guaranteeing constant paralleling of the outer secondaries, you basically "protect" the mid secondaries and then you can series connect them without trouble.
A cheat around options works quite good with the S-P-S-P-S setting. Make the outer S windings 1/2 of the internal ones, for example 1R, and the inner winding 4R. That respect the leakage inductance rule. Then connect the 1R windings in parallel, let them stay that way. It is better to have distant secondary layers in parallel. Then you can connect the 1R package with the 4R in series for a 9R output impedance.
A simple rule of thumb that worked for me the most of the time is to parallel secondaries with a big physical distance and also large Cps difference.
If you have to connect two secondaries in series, paralleling them to an already parallel package (impedances need to be equal of course) also helps big time.
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Thank you so much 50AE for all your help, I wish you will write all your experience about OPTs some day.
Thanks for recommending. It's true I spent a decade of sweat and hair pulling when studying audio transformers. Writing a book is a dream, however I'd like it to be elaborate and understandable by common folks, perfectly, with a practical example on each lesson. That is, winding A, B, C coil examples for each interleaving and idea, and there are tenths of them. It would be probably wise to break the book idea into smaller articles at first.
Here's a drawback to capacitance optimization and distribution though - it requires more manufacturing work. For example, dumping capacitance into the primary requires to split the primary packages into smaller ones and reconnecting them, instead of one consecutive winding. I believe it is a primary reason many manufacturers don't develop such ideas, to save on labor costs.
Here's an idea of how to dump capacitance for a S-P-S configuration. Instead of.
---------------S-----------
////////////////////////////// - Cpsf = negl.
B+------------P1----------g
f--------------P2----------g
f--------------P3----------e
d-------------P4----------e
d-------------P5----------c
b-------------P6----------c
b-------------P7----------a
Anode-------P8----------a
///////////////////////////// - Cpsf = 0,88
---------------S-----------
You can do the snail winding technique, however, all primary layers except for the inner two need to have outer connections. Primary capacitance increases 4 times, however the bottom p/s interface capacitance becomes negligible.
---------------S-----------
////////////////////////////// - Cpsf = negl.
B+------------P1----------g
f--------------P3----------e
d-------------P5----------c
b-------------P7----------a Cp = 4x times compared to sch. 1
Anode-------P8----------a
b-------------P6----------c
d-------------P4----------e
f--------------P2----------g
///////////////////////////// - Cpsf = 0,035
---------------S-----------
An easier compromise, which I often use, is splitting the primary only in two, reverse wind the first (anode half), so that the anode layer starts in the middle. This adds a capacitance primary to primary factor of 0.25, so you could add more dielectric thickness there. If you wish to redirect more capacitance to the primary, you could split the primary into 5/3 instead of 4/4
---------------S------------
////////////////////////////// - Cpsf = negl.
B+------------P1----------g
f--------------P2----------g
f--------------P3----------e
d-------------P4----------e
----------------------------- Cpf = 0,25
Anode-------P8----------a
b-------------P7----------a
b-------------P6----------c
d-------------P5----------c
///////////////////////////// Cpsf = 0,032
---------------S-----------
For further Cps reduction can be the splitting of the primary into 2/4/2, like this. This adds two Cpf of 0.25. P3 and P4 are reverse wound.
---------------S------------
////////////////////////////// - Cpsf = negl.
B+------------P1----------g
f--------------P2----------g
---------------------------- - Cpf = 0,25
d-------------P5----------c
b-------------P6----------c
b-------------P7----------a
Anode-------P8----------a
---------------------------- - Cpf = 0,25
d-------------P4----------e
f--------------P3----------e
///////////////////////////// Cpsf = 0,1
---------------S-----------
If you understand this lesson, you can use the same technique for other interleaving settings.
Bonus. Here are practical measurements of interleaving schematic 1 vs schematic 2.
Here's a drawback to capacitance optimization and distribution though - it requires more manufacturing work. For example, dumping capacitance into the primary requires to split the primary packages into smaller ones and reconnecting them, instead of one consecutive winding. I believe it is a primary reason many manufacturers don't develop such ideas, to save on labor costs.
Here's an idea of how to dump capacitance for a S-P-S configuration. Instead of.
---------------S-----------
////////////////////////////// - Cpsf = negl.
B+------------P1----------g
f--------------P2----------g
f--------------P3----------e
d-------------P4----------e
d-------------P5----------c
b-------------P6----------c
b-------------P7----------a
Anode-------P8----------a
///////////////////////////// - Cpsf = 0,88
---------------S-----------
You can do the snail winding technique, however, all primary layers except for the inner two need to have outer connections. Primary capacitance increases 4 times, however the bottom p/s interface capacitance becomes negligible.
---------------S-----------
////////////////////////////// - Cpsf = negl.
B+------------P1----------g
f--------------P3----------e
d-------------P5----------c
b-------------P7----------a Cp = 4x times compared to sch. 1
Anode-------P8----------a
b-------------P6----------c
d-------------P4----------e
f--------------P2----------g
///////////////////////////// - Cpsf = 0,035
---------------S-----------
An easier compromise, which I often use, is splitting the primary only in two, reverse wind the first (anode half), so that the anode layer starts in the middle. This adds a capacitance primary to primary factor of 0.25, so you could add more dielectric thickness there. If you wish to redirect more capacitance to the primary, you could split the primary into 5/3 instead of 4/4
---------------S------------
////////////////////////////// - Cpsf = negl.
B+------------P1----------g
f--------------P2----------g
f--------------P3----------e
d-------------P4----------e
----------------------------- Cpf = 0,25
Anode-------P8----------a
b-------------P7----------a
b-------------P6----------c
d-------------P5----------c
///////////////////////////// Cpsf = 0,032
---------------S-----------
For further Cps reduction can be the splitting of the primary into 2/4/2, like this. This adds two Cpf of 0.25. P3 and P4 are reverse wound.
---------------S------------
////////////////////////////// - Cpsf = negl.
B+------------P1----------g
f--------------P2----------g
---------------------------- - Cpf = 0,25
d-------------P5----------c
b-------------P6----------c
b-------------P7----------a
Anode-------P8----------a
---------------------------- - Cpf = 0,25
d-------------P4----------e
f--------------P3----------e
///////////////////////////// Cpsf = 0,1
---------------S-----------
If you understand this lesson, you can use the same technique for other interleaving settings.
Bonus. Here are practical measurements of interleaving schematic 1 vs schematic 2.
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