Hello everyone, I am currently implementing UAC2 on STM32F446RE. Now it supports up to PCM 352.8k and DSD64(DoP). Please give it a shot if you are interested.
Source code
PCB
Source code
PCB
Well done!
Couple of comments from quick glance:
Couple of comments from quick glance:
- Instead of PLL it would be better to use external clocks for MCK. STM32F466 allows this through I2S_CKIN (PC9).
- SAI would probably be more future-proof than I2S as with F7 & H7 SAI is much more evolved and feature-rich than I2S.
- The limits for async feedback at 44k1 (and multiples) are not symmetric as is the case with 48k (and multiples). This is not a huge issues as host just discards feedback that is not within limits.
- I assume this is intended to be similar to Amanero. Still I would add isolators for all output signals.
@bohrok2610 : IIUC the two I2S interfaces have their clock pins connected, and I2S3 is master while I2S1 is slave. The two interfaces should run synchronously if started closely to each other, IMO. Or can there be some race condition?
Based on the reference manual I'm not sure if master and slave data (in this case DSDL and DSDR) is synchronized so there may be slight timing offset between DSDL and DSDR. That probably does not matter. But since SAI provides synchronization and I2S has no real benefits why not just use SAI.
Hi bohrok2610,
- In a early version it is implemented as you said but I removed it as I did not think it is necessary. Maybe for lower clock jitter?
- The first comes to my mind is indeed SAI. Unfortunately, on 64-pin devices it collides with ULPI signals.
- As for synchronization between two I2S's, it is similar to I2S full duplex mode but the slave is also transmitting. The RM said in this case, they are synchronized by WS, as long as the slave is started before master. On oscilloscope I also did not observe any delay between two channels.
Much lower jitter is possible with external clocks but this of course depends on the clocks. Also fs frequency would be exact without error.
LQFP100 has SAI2A&B available.
Currently two. Theoretically the USB code can do more, but it would require external CPLD to handle channel splitting.
The clock is actually exact. 44.1k is 147/160 of 48k. I2S_SetFreq() in usbd_audio_if.c handles this case.
The 64-pin chip probably does not have available I2S or SAI interface. But suitable FW exists already:
https://www.diyaudio.com/community/threads/uac2-i2s-input-on-stm32f723e-disco.393702/
https://www.diyaudio.com/community/threads/uac2-i2s-input-on-stm32f723e-disco.393702/
Currently not. As it will require composite device support, which the library does not provide.
No composite device required but as I said 64-pin device with ULPI is out of suitable interfaces.
IMO best STM32 chip for this purpose would be 100-pin STM32F723VETx. It has built in HS PHY so no ULPI required. Also 2 SAI interfaces (SAI1_A, SAI2_B) available at one side of the chip for audio duplex operation (DAC & ADC). Cost of STM32F446 with ULPI is about the same but the chip is less capable.
Actually I would have preferred to use STM32F723VETx when I made my first USB-I2S bridge in 2021. Unfortunately back then it was not available so I had to use the 144-pin STM32F723ZETx which just wastes PCB real estate and leaves loads of GPIOs unused.
IMO best STM32 chip for this purpose would be 100-pin STM32F723VETx. It has built in HS PHY so no ULPI required. Also 2 SAI interfaces (SAI1_A, SAI2_B) available at one side of the chip for audio duplex operation (DAC & ADC). Cost of STM32F446 with ULPI is about the same but the chip is less capable.
Actually I would have preferred to use STM32F723VETx when I made my first USB-I2S bridge in 2021. Unfortunately back then it was not available so I had to use the 144-pin STM32F723ZETx which just wastes PCB real estate and leaves loads of GPIOs unused.
This is easily achievable as I2S_CKIN and RCC_MCO2, which is used as MCK output, are the same pin.
I2S does not have synchronization between interfaces so I2S input & output would be asynchronous (i.e. 2x half duplex). Synchronization with I2S could be done with external MCK assuming same clock is used in both DAC & ADC.