Ok trying to understand I2S over HDMI???

Gang,
So ok I understand the idea of HDMI connector for I2S as it does include 4 separate differential pairs. Ok so MCLK, SCLK, WCLK and DATA.

Back in the beginning of digital we all were doing some pretty weird stuff to make SPDIF better. We went as far as sending the Master Clock from the DAC to the transport and letting the transport derive the SPDIF from the received MCLK.

So in the HDMI setup is the transport/streamer sending all four of the signals or is the DAC sending the MCLK and the transport/streamer creating the I2S from the received MCLK?

Ok so this is LVDS differential pairs and I guess the dac either uses differential receivers like RS485 or transformers to convert to single ended.

We all know that putting the MCLK as close to the DAC chip as possible is the best avenue. But what about reclocking? Now you have the distance of the supplied cable which you don't know and yes you could apply 2x-8X MCLK for reclocking and that would work better for the SCLK, WCLK and DATA.

But really is this a good idea?

Please tell me the benefit of using I2S? Is it because the XMOS USB to I2S is so poor? I would think asynchronous USB would be much better than using a protocol like I2S intended for inches over a cable and a bunch of interconnects.

Thanks,
Gordon
 
They are all differential pair signalling, USB, HDMI, FireWire, Ethernet, DVI, RX485 because differential pairs work really well - eventually at long range the amplitude drops, external noise breaks in, and thus S/N degrades, which leads to extra jitter beyond the active devices' contributio, but that will apply the same whatever fabric is used.

Clock regeneration with a PLL is one way to undo the damage, but unlikely to be useful for short runs for audio, jitter just isn't that bad with high speed LVDS devices (these can handle of the order of a gigabaud, so jitter and skew are tiny compared to audio sample period)

I think any situation involving hauling signals over cables (rather than intra-board) the clock and the signals all go in the same direction, otherwise you'd have nightmare skew issues.

Note that optical emitters and receivers for SPDIF are often poor performers compared to LVDS, unless you upgrade to comms. grade devices with the high cost.
 
Guys!!!!!!
First yes I know I2S was developed for PCB use. I have been doing it since it was developed.
I also understand differential pairs as I was an engineer on 10/100 Ethernet got off that when they started talking about 4 bit half duplex which to me seemed really stupid.
Was asked to be on USB day 1 back in the 80's. Said why we have full duplex now, why are you doing 1/2 duplex USB. Of course now they admit they are wrong with SS/3 USB.
PLL's are ok and all the math says the inherent jitter input will equal the output. My symetricon says differently. One of the reasons why I don't get these expensive 10Mhz Master Clocks???
I want to know two things:
1) Is the MCLK pair coming from the DAC and if so how it is signaled to know even or odd?
2) What is the benefit of doing I2S over a cable, compared to USB Asynchronous?
Look I helped write the async protocol in 2002. It makes total sense.... unless your using a platform that creates jitter.
Thanks,
Gordon
 
What do you think about this device?


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