Non-feedback parametric linearisation in FETs

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x-pro

x-pro

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Joined 2003
ant-audio.co.uk
#1
This is my small Christmas present for those who like zero NFB single-ended class A amplification 🙂

I've worked in my spare time (for last year and half) on a home project to make a very linear single-ended transistor amplifier without NFB and one of my ideas I've described in a small article on my web site here:

http://www.ant-audio.co.uk/Theory/Parametric_Linearisation.htm

The performance of this circuit, despite the simplicity of the concept, is quite impressive - here is one example:

For a voltage amplifier stage using this idea I've measured distortion levels vs RMS current in the load resistor. Idle DC current was 4.5 mA, for 0.15 mA RMS current THD were 0.0025%, for 0.5 mA - 0.03%, for 1.15mA RMS (that is a swing from 3 to 6 mA (!) ) - only 0.16% .

It is possible to make this approach work even without the source resistor, thought it requires very careful transistors selection. THe circuit of my headphone amplifier (A.N.T. Audio "Amber") includes a voltage amplifier stage based on this idea.

Merry Christmas and Happy New Year!

Alex Nikitin
 
#3
#9
Very interesting indeed. To avoid opamps some I/V converters for DACS use valves. They rely on something like a 50 ohm resistor to ground followed by a valve voltage amplification stage. Would you say this topology is suitable for this purpose? That would be great, because few CD players have space for valve stages.
 
#10
Hennie said:
Very interesting indeed. To avoid opamps some I/V converters for DACS use valves. They rely on something like a 50 ohm resistor to ground followed by a valve voltage amplification stage. Would you say this topology is suitable for this purpose? That would be great, because few CD players have space for valve stages.
Click to expand...

This topology can be used in many applications, including this one 🙂 . For 50 Ohm and, say, FS 1 mA RMS output current of the DAC, the maximum input voltage would be 50 mV - near the "sweet spot" for this circuit, with a possibility of a very decent performance - with the distortions about 0.002% (mostly 2-nd order) and SNR about 100 dB.

Alex
 
#15
smoking-amp said:
Hi Alex,

Interesting circuit. Isn't the top Fet still operating in the pinch-off region with high output impedance?

Don
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Hi Don,

The top FET is operating with high output impedance, and this is a good thing 🙂 - as it allows for high gain if necessary, and if you need a lower output impedance you can just connect a smaller resistor as a load.

Alex
 
#18
Bricolo said:
and with mosfets?
Click to expand...

Why not? Perhaps not with all MOSFETs equally well and there are possible problems to be addressed with power FETs - i.e. input capacitance would be high with such a low drain voltage, biasing arrangement would not be trivial etc. However I plan to try this idea for a SE MOSFET power amplifier when I'll have time. As you may see from my first post, it is possible to have low distortion even when the drain current amplitude is very high (in relation to the idle DC current) , so this approach would be useful in a SE power amplifier.

Alex
 
#19
Very Nice Alex! 🙂

Have you used same devices for both upper and lower FET's?

Which device is benefiting most of your approach, the upper or lower FET, or maybe this approach can't be divided in to which device is benefiting of it?

Could this be done with lower device consisting of a FET and upper device of a BJT, and even vice verse lower BJT/upper FET?


Michael
 
#20
Ultima Thule said:
Very Nice Alex! 🙂
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Thank You!

Ultima Thule said:
Have you used same devices for both upper and lower FET's?
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It is possible, however I've found that with a right selection of two different devices the linear part of the characteristic could be made longer

Ultima Thule said:
Which device is benefiting most of your approach, the upper or lower FET, or maybe this approach can't be divided in to which device is benefiting of it?
Click to expand...

In this circuit the "lower" FET is the beneficiary, the "upper" FET is working hard to provide this benefit 🙂 .

Ultima Thule said:
Could this be done with lower device consisting of a FET and upper device of a BJT, and even vice verse lower BJT/upper FET?

Michael
Click to expand...

Not really, as you need a specific fit of two curves to linearise the transfer characteristic of the "lower" device. With FETs, both JFETs and MOSFETs it works, however BJTs are completely different beasts 🙂

Alex
 
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