Is this to be sandwiched between a pi & any Dac hat? To give better i2s to the Dac's PLL?
What about the Hat's that reclock already like Hifiberry Dac+ PRO & Digi+, and the pi2design prototype SPDIF board, would it be redundant?
What about the Hat's that reclock already like Hifiberry Dac+ PRO & Digi+, and the pi2design prototype SPDIF board, would it be redundant?
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Hi ,
yes the reclocker is between RPI and DAC.What it does is to buffer the DATA in memory and then reclocks i2s (outside FPGA) for the lowest jitter possible . We used an oscilloscope with a 2ps jitter floor and we have a reading of 3.081ps (rms) after buffer ..so very close to jitter floor, we will update this.We are using original NDK oscillators that are fed using pi filter and LDOs for a really clean power supply.
Now DAC+ pro has 2 xtals and operates in master mode. Its a good unit but definitely jitter wont be at the same (low) level.
In addition since we expose all i2s signals you will be able to use it with any outside DAC that you might have
yes the reclocker is between RPI and DAC.What it does is to buffer the DATA in memory and then reclocks i2s (outside FPGA) for the lowest jitter possible . We used an oscilloscope with a 2ps jitter floor and we have a reading of 3.081ps (rms) after buffer ..so very close to jitter floor, we will update this.We are using original NDK oscillators that are fed using pi filter and LDOs for a really clean power supply.
Now DAC+ pro has 2 xtals and operates in master mode. Its a good unit but definitely jitter wont be at the same (low) level.
In addition since we expose all i2s signals you will be able to use it with any outside DAC that you might have
In addition since we expose all i2s signals you will be able to use it with any outside DAC that you might have
Are you exposing MCLK as well as BCLK, LRCLK, DATA?
Sent you a PM about testing a board.
Hi ,
yes the reclocker is between RPI and DAC.What it does is to buffer the DATA in memory and then reclocks i2s (outside FPGA) for the lowest jitter possible . We used an oscilloscope with a 2ps jitter floor and we have a reading of 3.081ps (rms) after buffer ..so very close to jitter floor, we will update this.We are using original NDK oscillators that are fed using pi filter and LDOs for a really clean power supply.
Now DAC+ pro has 2 xtals and operates in master mode. Its a good unit but definitely jitter wont be at the same (low) level.
In addition since we expose all i2s signals you will be able to use it with any outside DAC that you might have
Hi cdsgames,
This is exciting stuff, can you stack reclocking boards on your board, give it a better source, or at least let it work transparently to try it out?
I'll link some threads from SBAF... a bunch of us are discussing, testing a prototype spdif board that's fairly advanced with it's power and clocking (it's a 4-layer board, pi ground filtering, many separate LDO's etc)
(and I'll link back to here... sure they will be interested.)
Also have been using piZERO, digi+, dac+pro, LDO -- to get the most out of it.
I'd def. be interested in a test board!
Thanks!
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@cdsgames
Just FYI if you'd like to skim thru these quick, I'll just drop you in the middle somewhere 😀
(My username is Scott Kramer there)
Link: SBAF pi digi+
Michael Kelly designed & built that spdif board (still just prototype) he has a few out testing.
Link: SBAF advanced digital hat
Just FYI if you'd like to skim thru these quick, I'll just drop you in the middle somewhere 😀
(My username is Scott Kramer there)
Link: SBAF pi digi+
Michael Kelly designed & built that spdif board (still just prototype) he has a few out testing.
Link: SBAF advanced digital hat
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Hi cdsgames,
This is exciting stuff, can you stack reclocking boards on your board, give it a better source, or at least let it work transparently to try it out?
Thanks!
Staking multiple reclocker wont improve anything...the clocks are discarded in the FPGA and a new clock its provided. Basically source has no value on i2s (our board) output
Staking multiple reclocker wont improve anything...the clocks are discarded in the FPGA and a new clock its provided. Basically source has no value on i2s (our board) output
No, No 😀 I meant existing reclocking (maybe thats the wrong term, master mode) Dac's like the D+PRO, will they work...
No they wont...frankly speaking a DAC that takes the 3.3v directly from RPI might be ok for some users...but not what we designed.
Our reclocker has better jitter than 3ps (and trust me it took a lot of filtering m LDOs and placement of capacitors to reach it) and you can feed that to our DAC (2.1)
http://www.diyaudio.com/forums/digital-line-level/295128-new-dac-rpi-subwoofer-out-2-1-2-2-a.html . We use 2 separate LDOs (digital and a very expensive LDO for analog). The digital filters (4 poles) reveal another layer of the recorded music...
The sound is..hard to describe. But yeah you need good speakers and a subwoofer .
Our reclocker has better jitter than 3ps (and trust me it took a lot of filtering m LDOs and placement of capacitors to reach it) and you can feed that to our DAC (2.1)
http://www.diyaudio.com/forums/digital-line-level/295128-new-dac-rpi-subwoofer-out-2-1-2-2-a.html . We use 2 separate LDOs (digital and a very expensive LDO for analog). The digital filters (4 poles) reveal another layer of the recorded music...
The sound is..hard to describe. But yeah you need good speakers and a subwoofer .
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Interesting board! 🙂
How do you control volume? Do you use the PCM5142's hardware volume control?
How do you control volume? Do you use the PCM5142's hardware volume control?
I checked for Odroidc2...unfortunately it has a different i2s output.
Can we pull wires from Odroid C2 I2S pins and feed it to your FIFO buffer board?
Yes..of course we could use the DSPs volume control but it has no advantage and it takes some DSP cycles
Interesting board! 🙂
How do you control volume? Do you use the PCM5142's hardware volume control?
Of course you can...but let me look it over tomorrow with our designers...its in our advantage to have it compatible with as many SBCs as possible.
Can we pull wires from Odroid C2 I2S pins and feed it to your FIFO buffer board?
No they wont...frankly speaking a DAC that takes the 3.3v directly from RPI might be ok for some users...but not what we designed.
Our reclocker has better jitter than 3ps (and trust me it took a lot of filtering m LDOs and placement of capacitors to reach it) and you can feed that to our DAC (2.1)
http://www.diyaudio.com/forums/digital-line-level/295128-new-dac-rpi-subwoofer-out-2-1-2-2-a.html . We use 2 separate LDOs (digital and a very expensive LDO for analog). The digital filters (4 poles) reveal another layer of the recorded music...
The sound is..hard to describe. But yeah you need good speakers and a subwoofer .
Got it, interesting Dac, I have a pair of ML Descent i's
Interesting board! 🙂
How do you control volume? Do you use the PCM5142's hardware volume control?
Good point... how the heck do you control the sub volume?
there are 2(1/2) scenarios:
Control of sound by DAC (AMP at fixed volume)
In that case both soft volumes can move in tandem (subwoofer can even be specified at % of LR volume)
Control of sound by AMP (DAC at max) .
We suggest to keep the volume of the SUB at a lower level (enough for most situations)..control on LR with your AMP. The sub will only supplement some bass.
most used scenario...we keep the volume of the AMP somewhere in the middle and we control the volume (a bit higher or lower) using 1 scenario.
Control of sound by DAC (AMP at fixed volume)
In that case both soft volumes can move in tandem (subwoofer can even be specified at % of LR volume)
Control of sound by AMP (DAC at max) .
We suggest to keep the volume of the SUB at a lower level (enough for most situations)..control on LR with your AMP. The sub will only supplement some bass.
most used scenario...we keep the volume of the AMP somewhere in the middle and we control the volume (a bit higher or lower) using 1 scenario.
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