New Analog Device clock distribution and generation, with 225fs jitter!

[Bricolo]

225 femtosecond! but in 12kHz-20MHz

here:
http://www.analog.com/en/subCat/0,2879,770%5F931%5F0%5F%5F0%5F,00.html

 

[bitrate]

When using PLL circuits main jitter performance is dependent of the jitter generated by VCXO.Look at this document:
http://focus.ti.com/docs/apps/catalog/resources/appnoteabstract.jhtml?abstractName=scaa067
It is jitter spec. of Ti CDC7005 with diferent VCXO's When acting as a buffer 1:1 ,jitter added to signal is only 11fs . Good low noise VCXO may cost much much more than 200$
Regards

 

[Guido Tent]

225 femtosecond! but in 12kHz-20MHz

here:
http://www.analog.com/en/subCat/0,2879,770%5F931%5F0%5F%5F0%5F,00.html

Hi

The short term jitter is of importance, but it is not that difficult to make that low. Ofcourse 12kHz jitter content is not that interesting.

The LF and sub LF counts when it comes to audibility, as the ear is much more sensitive there.

cheers