Hi all,
I'm troubleshooting my AD1853, and I've got DC-offset problem.
I've measured the output DC on each side of the differential I/V convertors, one is 7.09V and the other is 7.21V. So, after the differential to single-end stage, I've got 120mVdc!! (I've used 2.67Kohm Iref resistor as stated in the datasheet.)
From what I've understand from the datasheet, there should be 1mA bias current sinking into each Iout. And I/V convertors are having 2.75V voltage bias at their non-inverting inputs. I'm using 4.3Kohm I/V resistor. So I expect the 7Vdc is coming from this.
3.9Kohm*1mA + 2.75V = 6.65V
It seems to me that the bias current sinking into each Iout are not balanced. However, the output AC on each side of the I/V are well matched. Is this true?? Am I missing something?
Thanks in advance.
I'm troubleshooting my AD1853, and I've got DC-offset problem.
An externally hosted image should be here but it was not working when we last tested it.
I've measured the output DC on each side of the differential I/V convertors, one is 7.09V and the other is 7.21V. So, after the differential to single-end stage, I've got 120mVdc!! (I've used 2.67Kohm Iref resistor as stated in the datasheet.)
From what I've understand from the datasheet, there should be 1mA bias current sinking into each Iout. And I/V convertors are having 2.75V voltage bias at their non-inverting inputs. I'm using 4.3Kohm I/V resistor. So I expect the 7Vdc is coming from this.
3.9Kohm*1mA + 2.75V = 6.65V
It seems to me that the bias current sinking into each Iout are not balanced. However, the output AC on each side of the I/V are well matched. Is this true?? Am I missing something?
Thanks in advance.
A typo in my last post, I'm using 3.9K I/V resistors.
After reading the datasheet again and again, I'm getting more confused above the output bias current of AD1853.....
On page2 of AD1853 datasheet, it saids, "DC gain error: +/-3%"
And on page10, "The analog ouput is usually ac coupled with a 10uF capacitor".
Till I read the AD1955 datasheet, I've finally got some more explaination about the DC bias current. The pull up resistor calculation on page13 of AD1955 datasheet comfirmed my assumption about the common mode DC.
By calculation, only 1.5% of bias mismatch would be enough to yield the 120mV DC-offset in my case....
I followed the pull up resistor calculation. End up using 6.8K pull up to +15V rail. The common mode DC reduced from 7.1V to 0.27V. And by fine trimming one of the pull up resistor on each R/L channel, the final DC offset is nulled to within +/-2mV.
The final DC-offset settle very slowly during startup, something like one or two minutes. And there is some long term drift too. This offset trimming approach is certainly not as good as servo or coupling capacitor. But I'll settle on this first.
I wondered other AD1853 builder also have similar experience??
After reading the datasheet again and again, I'm getting more confused above the output bias current of AD1853.....
On page2 of AD1853 datasheet, it saids, "DC gain error: +/-3%"
And on page10, "The analog ouput is usually ac coupled with a 10uF capacitor".
Till I read the AD1955 datasheet, I've finally got some more explaination about the DC bias current. The pull up resistor calculation on page13 of AD1955 datasheet comfirmed my assumption about the common mode DC.
By calculation, only 1.5% of bias mismatch would be enough to yield the 120mV DC-offset in my case....
I followed the pull up resistor calculation. End up using 6.8K pull up to +15V rail. The common mode DC reduced from 7.1V to 0.27V. And by fine trimming one of the pull up resistor on each R/L channel, the final DC offset is nulled to within +/-2mV.
The final DC-offset settle very slowly during startup, something like one or two minutes. And there is some long term drift too. This offset trimming approach is certainly not as good as servo or coupling capacitor. But I'll settle on this first.
I wondered other AD1853 builder also have similar experience??
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