I want to hang a current source at the positive rail to drive an input diff pair, and would like to use JFET's for that.
The Siliconix Application Note AN103 showed circuits using N-FET's as current source (e.g. J202, J505, etc.), but they were all placed at the bottom end, with the gate and the source resistor tied to the negative rail, and the drain to the load -- i.e. a current sink.
I wonder if there is any reason why one cannot tie the drain to the positive rail, and the source resistor / gate to the load instead.
Any expert advices most welcome.
Many thanks,
Patrick
The Siliconix Application Note AN103 showed circuits using N-FET's as current source (e.g. J202, J505, etc.), but they were all placed at the bottom end, with the gate and the source resistor tied to the negative rail, and the drain to the load -- i.e. a current sink.
I wonder if there is any reason why one cannot tie the drain to the positive rail, and the source resistor / gate to the load instead.
Any expert advices most welcome.
Many thanks,
Patrick
It is the constant voltage across the resistor that makes
the device a current source. The voltage from the gate
to the minus rail is fixed hence the voltage across the
resistor is fixed hence the constant current.
If you want a current source from the top rail, turn
the whole thing upside down and use a p channel fet
instead.
the device a current source. The voltage from the gate
to the minus rail is fixed hence the voltage across the
resistor is fixed hence the constant current.
If you want a current source from the top rail, turn
the whole thing upside down and use a p channel fet
instead.
Patrick, I use N-JFETs both like current sources and current sinks. Not in the application you mentioned though, but I'd say no problem with it.
jfet current source
What you propose should work. Another solution is to mirror image the AN-103 circuit vertically and use a p-channel JFET. The load resistance is at ground and the circuit is sourcing current. You must select the proper values for resistance to keep the JFET biased inside its active region with either circuit. The Vdd power supply must be high enough to provide sufficient Vds, and Vgate is a few volts below Vsource (n-channel JFET). Also, JFET parameters vary quite a bit. A large value of source resistor minimizes this variation's effect at the expense of reducing overall current. I hope this helps. Best regards.
What you propose should work. Another solution is to mirror image the AN-103 circuit vertically and use a p-channel JFET. The load resistance is at ground and the circuit is sourcing current. You must select the proper values for resistance to keep the JFET biased inside its active region with either circuit. The Vdd power supply must be high enough to provide sufficient Vds, and Vgate is a few volts below Vsource (n-channel JFET). Also, JFET parameters vary quite a bit. A large value of source resistor minimizes this variation's effect at the expense of reducing overall current. I hope this helps. Best regards.
N-FET or P-FET
The problem I have with P-JFET is that they have 10 times more noise (J174 compared to J111), which is why I asked.
I have also tried hanging the N-FET circuit on the top rail without problems (i.e. I still get a current source), but want to know if there are any disadvantageswhen used in my particular application. So the question is, would you rather live with the noise with aP-JFET, or N-JFET hanging "up side down" ?
Or can someone suggest a low-noise P-JFET's with Idss of 20 - 100 mA and noise level of about 1 nV ^/Hz ?
Patrick
The problem I have with P-JFET is that they have 10 times more noise (J174 compared to J111), which is why I asked.
I have also tried hanging the N-FET circuit on the top rail without problems (i.e. I still get a current source), but want to know if there are any disadvantageswhen used in my particular application. So the question is, would you rather live with the noise with aP-JFET, or N-JFET hanging "up side down" ?
Or can someone suggest a low-noise P-JFET's with Idss of 20 - 100 mA and noise level of about 1 nV ^/Hz ?
Patrick
FET current sources
The Siliconix current sources are two terminal devices that work fine from either rail. How much current do you need? I have had good results paralleling them for higher current.
Building one with a Jfet and resistor also works, since thats what is inside the two terminal devices. And there is no need to use a P-Jfet. The electrons really don't know which end is tied to a supply.
-Demian
The Siliconix current sources are two terminal devices that work fine from either rail. How much current do you need? I have had good results paralleling them for higher current.
Building one with a Jfet and resistor also works, since thats what is inside the two terminal devices. And there is no need to use a P-Jfet. The electrons really don't know which end is tied to a supply.
-Demian
Japanese manufacturer Semitec-Ishizuka makes two-terminal CRDs in values of up to 15mA, in axial leaded (like a small-signal diode) as well as surface-mount LLD packaging.
pdf catalog here:
http://www.semitec.co.jp/pdf/productE/proEALL.pdf
hth, jonathan carr
pdf catalog here:
http://www.semitec.co.jp/pdf/productE/proEALL.pdf
hth, jonathan carr
Cascode ?
Thank you for the info.
I would need 30mA with about 15V across the current source, and am actually considering a cascoded JFET source.
P-FET Version:
4 x (2SJ74V cascoded by J174, with source resistor to set Id @ 7.5mA each)
N-FET Version:
4 x (2SK170V cascoded by J111, with source resistor to set Id @ 7.5mA each)
In my understanding, the current is controlled by the "lower"FET -- in this case the two Toshiba's. Both the 2SK170 and the 2SJ74 has similarly low noise figures, so my guess is that it doesn't matter so much if the cascoding FET (J174 or J111) has a bit of noise. But then it doesn't do any harm to use the one with a much lower noise (J111), if the N-FET version works equally well as a P-FET version when hung directly on the + rail.
Is my interpretation correct ?
Patrick
Thank you for the info.
I would need 30mA with about 15V across the current source, and am actually considering a cascoded JFET source.
P-FET Version:
4 x (2SJ74V cascoded by J174, with source resistor to set Id @ 7.5mA each)
N-FET Version:
4 x (2SK170V cascoded by J111, with source resistor to set Id @ 7.5mA each)
In my understanding, the current is controlled by the "lower"FET -- in this case the two Toshiba's. Both the 2SK170 and the 2SJ74 has similarly low noise figures, so my guess is that it doesn't matter so much if the cascoding FET (J174 or J111) has a bit of noise. But then it doesn't do any harm to use the one with a much lower noise (J111), if the N-FET version works equally well as a P-FET version when hung directly on the + rail.
Is my interpretation correct ?
Patrick
Input pair current
What are you using for an input pair that needs so much current? At 30 mA you will increase the noise of almost all Jfets and a BJT at that current will have an almost unuseable input current (not to mention noise).
I would cascode with a powerfet.
-Demian
What are you using for an input pair that needs so much current? At 30 mA you will increase the noise of almost all Jfets and a BJT at that current will have an almost unuseable input current (not to mention noise).
I would cascode with a powerfet.
-Demian
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