I was wondering if you got any feed back on this device, did you like it in the end?
Did Pano test it? Could I build one?
Did Pano test it? Could I build one?
I am interested in the exact same thing. It looks very nice and I will have some chips available soon.
Has one tried the layout provided and followed the tips earlier posted?
Has one tried the layout provided and followed the tips earlier posted?
According to the TS, the layout is ok for him, but is not to us. I am still looking for a (single sided) layout for the chip.
I am currently "designing" a TPA3106 board, but I am not quite sure what to do with the Master/Slave setting. I think I need to put it high, but I am not 100% sure. Do any of you have experience with this?
It gets tied to VREG (Pin 10) for MASTER mode, or GND for SLAVE. SYNC (Pin 8) is an output in MASTER mode and an input in SLAVE mode.
On my mono boards they were both running in master mode and it didn't seem to cause any problems. If you put more than one IC on the same PCB it might be good to slave one of them.
On my mono boards they were both running in master mode and it didn't seem to cause any problems. If you put more than one IC on the same PCB it might be good to slave one of them.
Thanks, my first proto is coming soon. I just hope I interpreted the circuit in the datasheet correctly.
If you connect FAULT to MUTE the amp will automatically mute the outputs if there is a fault condition reported.
Hmmz, ok, nice tip!
Prototype #1 has been etched. This was the first attemp with a new UV source and different etching liquid so it's not looking great, but for a prototype it is acceptable. More is to come 🙂
Prototype #1 has been etched. This was the first attemp with a new UV source and different etching liquid so it's not looking great, but for a prototype it is acceptable. More is to come 🙂
Hi,
I see even in a precision PCB layers. good work.
Curve is very strange, it seems that a considerable delay with increasing frequency. You Have phase curves of this chip?
I see even in a precision PCB layers. good work.
Curve is very strange, it seems that a considerable delay with increasing frequency. You Have phase curves of this chip?
I am having some difficulties with the TPA3106 design. I had made this board, but it was deadsilent. The Vreg was ok, 4 volts, but other than that there was no sign of life. I think I tripple checked the SD and Mute settings. Would one of you check my design?
To avoid confusion; there is a +V jumper going over the chip, the large items on the right are my smd coils and the left groundplane is signal, the right is power and they "fuse" under the chip, as advised.
TPA3106.zip - download now for free. File sharing. Software file sharing. Free file hosting. File upload. FileFactory.com
http://focus.ti.com/lit/ds/symlink/tpa3106d1.pdf
To avoid confusion; there is a +V jumper going over the chip, the large items on the right are my smd coils and the left groundplane is signal, the right is power and they "fuse" under the chip, as advised.
TPA3106.zip - download now for free. File sharing. Software file sharing. Free file hosting. File upload. FileFactory.com
http://focus.ti.com/lit/ds/symlink/tpa3106d1.pdf
Your grounds should be analog and digital joined under the chip if you are going to split them at all. Quite often it is best not to split them and have one contigous ground plane, due to the high DI/DT switching currents.
Can you post a jpg of your layout? I don't use any programs that can view your files.
That is what I did, I have two planes which connect under the chip.
Here's a picture; ImageShack® - Online Photo and Video Hosting
I don't immediately see anything wrong in the pic. Double check there are no shorts between pins.
What type of bootstrap caps are you using (film or ceramic)?
BTW, your ground fill layout makes the main supply decoupling cap almost useless. Look at the path the current flows from the cap to the chip; way too long. There should be two caps of equal value, one on each side of the IC as close as possible to the pins. There should also be a >10uF cap as close the AVCC pin as possible.
What type of bootstrap caps are you using (film or ceramic)?
BTW, your ground fill layout makes the main supply decoupling cap almost useless. Look at the path the current flows from the cap to the chip; way too long. There should be two caps of equal value, one on each side of the IC as close as possible to the pins. There should also be a >10uF cap as close the AVCC pin as possible.
Last edited:
- Status
- Not open for further replies.