Hi,
This thread is for the purpose of discussing how miller capacitance, or other bandwidth limiting factors can increase/decreas the THD of an amplifier.
To what extent can an increase in Miller capacitance increase the distortion of an amplifier?
Reasoning would dictate that any decrease in frequency response, would slow an amplifiers ability to reproduce a signal at high frequencies, therefore increasing distortion. However, this reasong should also apply to a increase in distortion at lower frequencies because of a limiting of bandwidth.
Also consider that the RMS noise of an amplifier is porportional to bandwidth. Therefore, an increase in bandwidth should increase the noise floor of an amplifier. Would it be beneficial to increase bandwidth and noise, to reduce harmoic distortion?
Would an increase in miller capacitance increase Even and Odd harmonics equilly, or not?
-Dan
This thread is for the purpose of discussing how miller capacitance, or other bandwidth limiting factors can increase/decreas the THD of an amplifier.
To what extent can an increase in Miller capacitance increase the distortion of an amplifier?
Reasoning would dictate that any decrease in frequency response, would slow an amplifiers ability to reproduce a signal at high frequencies, therefore increasing distortion. However, this reasong should also apply to a increase in distortion at lower frequencies because of a limiting of bandwidth.
Also consider that the RMS noise of an amplifier is porportional to bandwidth. Therefore, an increase in bandwidth should increase the noise floor of an amplifier. Would it be beneficial to increase bandwidth and noise, to reduce harmoic distortion?
Would an increase in miller capacitance increase Even and Odd harmonics equilly, or not?
-Dan
If Miller capacitance in a fet increases as Vds swings down then I expect it would make even order distortion.
Increasing the miller-cap(reverse transfer cap), causes the loop-gain to decrease at high frequency.😎
Morello said:
...which in turn makes the feedback less effective (less excess gain available) which increases the THD. As for the low side of the spectrum, the bandwidth limiting is often outside of the feedback loop (like input cap) so does not decrease the available feedback, so would not in itself increase THD.
Jan Didden
Circlotron said:
I think the question was about using a stable design (stable because of inherent or externally added capacitance on the VAS stage) and then adding even more capacitance.
An external capacitance will not depend on the base collector voltage.
Yes, it will decrease open loop gain above the open loop corner frequency. This may be 500 Hz in a typical design and would move to 250 Hz if the total effective capacitance is doubled.
THD would in theory increase in proportion to the capacitance increase. But this is too simple. There are two more effects to be considered.
1) The external capacitance is largely independent of voltage whereas the internal is not. Having a much larger external than internal capacitance will linearize the total capacitance as a function of voltage and hence give an additional disto benefit.
2) The miller capacitance is a local feedback around the VAS transistor. This will decrease the output impedance of the VAS stage. Hence, it will be more immune to disto which comes from the nonlinear input impedance of the power output stage. Also, it'll move the pole of the output stage further out, making overall frequency compensation easier. However, one should use base stopper resistors or ferrite beads on the bases to avoid local osciallations.
Eric
Noting an Increase in THD...
I actually did a test the other day, to determine if more 'miller capacitance would increase THD. And, actually, it did.
With the amplifier running on the bench, increasing the Miller cap, I noted a harmonic frequency pop up out of the noise floor. It would dissappear again when I pulled the cap out. (Again, my amp is currently on a breadboard, so changes are quick)
My test frequency was 1Khz, with a little frequency peak at 2Khz. (This distortion is present at the input to the amplifier, and comes from my signal in my signal generator) Adding additional miller capacitance caused an increase in a third frequency (3Khz). At an amplifier output level of 2Vrms (1Khz sine), the 2khz harmonic is around .016mV rms. The third harmonic starts at about 2mV. Adding the miller capacitance increases that harmonic to around 9mV. This was with a change of 5pF to 100pF. (My external miller cap is in series with a 10K resistor)
If I remember this correctly, the THD calculated for each part of the test would be:
Small miller Cap: %THD = .81% THD
Large miller cap: %THD = .92% THD
So, an increase in THD of about .11% at 1Khz. (A good portion of this distortion is actually due distortion in the signal generator!)
Now, that added capacitance affected the phase at 1Khz by about -3 degrees. (And about -17 degrees at 10Khz). So in reality, the change in capacitance was a 'Large' increase.
While looking at the signal in voltage vs/time, it was noted that the extra capacitor caused a change in cross over distortion on the drive signal to the Class AB output stage. (Slowed the slew rate to of the signal to the output transistors)
Maybe an increase in bias current in the output devices would have minimized this distortion?
thoughts? comments?
-Dan
I actually did a test the other day, to determine if more 'miller capacitance would increase THD. And, actually, it did.
With the amplifier running on the bench, increasing the Miller cap, I noted a harmonic frequency pop up out of the noise floor. It would dissappear again when I pulled the cap out. (Again, my amp is currently on a breadboard, so changes are quick)
My test frequency was 1Khz, with a little frequency peak at 2Khz. (This distortion is present at the input to the amplifier, and comes from my signal in my signal generator) Adding additional miller capacitance caused an increase in a third frequency (3Khz). At an amplifier output level of 2Vrms (1Khz sine), the 2khz harmonic is around .016mV rms. The third harmonic starts at about 2mV. Adding the miller capacitance increases that harmonic to around 9mV. This was with a change of 5pF to 100pF. (My external miller cap is in series with a 10K resistor)
If I remember this correctly, the THD calculated for each part of the test would be:
Small miller Cap: %THD = .81% THD
Large miller cap: %THD = .92% THD
So, an increase in THD of about .11% at 1Khz. (A good portion of this distortion is actually due distortion in the signal generator!)
Now, that added capacitance affected the phase at 1Khz by about -3 degrees. (And about -17 degrees at 10Khz). So in reality, the change in capacitance was a 'Large' increase.
While looking at the signal in voltage vs/time, it was noted that the extra capacitor caused a change in cross over distortion on the drive signal to the Class AB output stage. (Slowed the slew rate to of the signal to the output transistors)
Maybe an increase in bias current in the output devices would have minimized this distortion?
thoughts? comments?
-Dan
Doesn't it depend on where the disto is coming from?
If it is coming from the VAS, then Miller capacitance can decrease disto, by locally linearizing the VAS.
If the distortion source is outside the VAS, then the reduction in loop gain from the Miller compensation makes it worse.
If the Miller capacitance causes excessive loading on the preceding stage, then it might increase disto, even causing slewing disto.
Or am I mixed up?
If it is coming from the VAS, then Miller capacitance can decrease disto, by locally linearizing the VAS.
If the distortion source is outside the VAS, then the reduction in loop gain from the Miller compensation makes it worse.
If the Miller capacitance causes excessive loading on the preceding stage, then it might increase disto, even causing slewing disto.
Or am I mixed up?
Miller etc
Mirlo,
There is yet another effect: if you decrease the miller cap, the Vas disto (I like that word) may increase, but because of the increase in open loop gain at higher freqs, the feedback gets more effective and it is possible that the total amp disto goes down. And I think you agree that that is the final goal.
Jan Didden
Mirlo,
There is yet another effect: if you decrease the miller cap, the Vas disto (I like that word) may increase, but because of the increase in open loop gain at higher freqs, the feedback gets more effective and it is possible that the total amp disto goes down. And I think you agree that that is the final goal.
Jan Didden
mirlo said:
I'd say this is all correct.
Without having done a simulation, I guess that in first order approximation, if and only if the VAS is the dominant disto contributor, overall disto is largely independent of the miller capacitance. What you loose in loop gain if mirrored by improvements from the local feedback loop.
If you look more closely, as I pointed out above, benefits from swamping the inherent miller capacitance and from pole splitting may tip the scale in favor of stronger local feedback.
Re: Noting an Increase in THD...
Do you have a 5 pF capacitor between B and C? And you paralleled that with the series connection of 100 pF and 10 k? Then your findings are not surprising. Even if you have the 10 k in series to both capacitors, it does not really change my argument.
1) If you are using a video transistor such as BF472, it will have an internal, voltage dependent Miller capacitance of 2-3 pF. The 5 pF gives some linearization, but not much. The 10 k prevents the 100 pF from doing any effective linearization. If you are using a typical 1-2 A transistor, you have to recon about 20 pF internal capacitance, so you have no linearization to speak of.
2) Peufeu would argue that you introduced a memory distortion source. Look up the thead. Even if I don't agree on all points, it makes interesting reading.
3) The 10 k prevents local feedback.
4) The 10 k makes for some really strange-looking Bode plot. At what frequencies you have how much of a change in loop gain depends on the impedances at the input and output of the VAS. I am pretty sure you won't benefit from pole splitting. Actually my guess is that 10 k is not much smaller than the impedance at the output, so this renders your compensation largely ineffective anyway.
Do you have a 5 pF capacitor between B and C? And you paralleled that with the series connection of 100 pF and 10 k? Then your findings are not surprising. Even if you have the 10 k in series to both capacitors, it does not really change my argument.
1) If you are using a video transistor such as BF472, it will have an internal, voltage dependent Miller capacitance of 2-3 pF. The 5 pF gives some linearization, but not much. The 10 k prevents the 100 pF from doing any effective linearization. If you are using a typical 1-2 A transistor, you have to recon about 20 pF internal capacitance, so you have no linearization to speak of.
2) Peufeu would argue that you introduced a memory distortion source. Look up the thead. Even if I don't agree on all points, it makes interesting reading.
3) The 10 k prevents local feedback.
4) The 10 k makes for some really strange-looking Bode plot. At what frequencies you have how much of a change in loop gain depends on the impedances at the input and output of the VAS. I am pretty sure you won't benefit from pole splitting. Actually my guess is that 10 k is not much smaller than the impedance at the output, so this renders your compensation largely ineffective anyway.
Re: Re: Noting an Increase in THD...
The whole point is for the thread to be interesting... ...as I actually had done the test before I started the thread.
The 5pF is in series with the 10K resistor. I just add the 100pF in parallel with the 5pF. (So, I get 105pF in series with 10K).
The transistor I'm using has about 30Pf BC, except it's a PNP and is part of a complementray pair configured as a high gain NPN. So the 'Miller Capacitance" is connected across the effective Base and Effective Collector. (Actually the Base of the first (NPN), and Emitter of the second (PNP) transistor.)
I selected the 5pF in series with the 10K specifically because it was VERY small, with little effect. This is exactly what I wanted. It is very stable, even if not completly 'damped'. With a step response signal, you see some ringing. But, I've never seen a 'step' in a music signal.
On to more theory....
Correct me if I'm wrong, but I think that it would be best to limit local NFB in the case of an amplifier with a complete feedback loop. (Open loop amps, this would be completley opposite)
It seems everyone wants to increase NFB in stages following the diff pair (to increse linearity). But, with a good matched pair of transistors, wouldn't the diff pair correct for the distortion in the following stages, and reduce the total distortion? Wouldn't you want very fast stages following the diff pair?
(I think this is what was basically posed in earlier posts)
So in reality, isn't this part of the design really a baliacing act to achieve stability and reduce disto by finding a happy medium value of external miller cap?
-Dan
capslock said:
The whole point is for the thread to be interesting... ...as I actually had done the test before I started the thread.
The 5pF is in series with the 10K resistor. I just add the 100pF in parallel with the 5pF. (So, I get 105pF in series with 10K).
The transistor I'm using has about 30Pf BC, except it's a PNP and is part of a complementray pair configured as a high gain NPN. So the 'Miller Capacitance" is connected across the effective Base and Effective Collector. (Actually the Base of the first (NPN), and Emitter of the second (PNP) transistor.)
I selected the 5pF in series with the 10K specifically because it was VERY small, with little effect. This is exactly what I wanted. It is very stable, even if not completly 'damped'. With a step response signal, you see some ringing. But, I've never seen a 'step' in a music signal.
On to more theory....
Correct me if I'm wrong, but I think that it would be best to limit local NFB in the case of an amplifier with a complete feedback loop. (Open loop amps, this would be completley opposite)
It seems everyone wants to increase NFB in stages following the diff pair (to increse linearity). But, with a good matched pair of transistors, wouldn't the diff pair correct for the distortion in the following stages, and reduce the total distortion? Wouldn't you want very fast stages following the diff pair?
(I think this is what was basically posed in earlier posts)
So in reality, isn't this part of the design really a baliacing act to achieve stability and reduce disto by finding a happy medium value of external miller cap?
-Dan
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