John Curl preamplifier JC-2 is a classic.
Here I use something like it for a power amplifier.
THD 0.0020% in simulation.
More than 20 Watt max.
Here I use something like it for a power amplifier.
THD 0.0020% in simulation.
More than 20 Watt max.
Last edited:
Oops, that hurts even more...
After 2nd look, the datasheets of LSJ689 may not be right. The input capacitance specs contradicts its chart. I think the chart number is more realistic.
vs
I haven't tried these JFETs yet. How big is the transconductance difference between N & P parts? I'm a little surprised lineup did not use EUVL's suggestion for adding degeneration resistors in the source of one polarity to help. I think Bob Cordell also used this trick in his Hafler 220C.
Note:
I have updated schematic in first post.
Added compensation capacitors 47pF.
This gives an upper frequency of 350kHz.
So we need no input filter now.
THD is still 0.0018%
I have updated schematic in first post.
Added compensation capacitors 47pF.
This gives an upper frequency of 350kHz.
So we need no input filter now.
THD is still 0.0018%
Using oscilloscope squarewave in SPICE I discovered that I needed to increase compensation.
Now there are two capacitors 150pF.
This makes the upper frequency is 150kHz.
THD is now 0.0019%
This can be seen in first post.
Now there are two capacitors 150pF.
This makes the upper frequency is 150kHz.
THD is now 0.0019%
This can be seen in first post.
@lineup , you have no source resistor between U2,3 - U5,6. The circuit will be extremely sensitive to Idss, Vp and Gm variations of the JFETs and will need either selection from many many parts or resistor changes for every piece built. Try to change these mentioned parameters in the simulator and see what is happening.
I have decded to make it Single Supply circuit.
This should eliminate any offset issues.
Data is the same:
THD 0.0019% and upper frequency 150kHz.
See first post!
This should eliminate any offset issues.
Data is the same:
THD 0.0019% and upper frequency 150kHz.
See first post!
In the real world you will have a lot of problems to solve before you reach such distortion levels with a single supply. The lower output transistor takes its half period current from the ground. A lot of distortion is build in.
And you need to have most of the signal feedback after the output capacitor to avoid the distortion from it. In the simulation the capacitor is ideal. In the real world far from that.
C10 makes nothing and you can save some money at the input if you use 3 x 100k resistors and a 100uF is probably enough.
What are C9 and R18 doing? Do you have different grounds?
And you need to have most of the signal feedback after the output capacitor to avoid the distortion from it. In the simulation the capacitor is ideal. In the real world far from that.
C10 makes nothing and you can save some money at the input if you use 3 x 100k resistors and a 100uF is probably enough.
What are C9 and R18 doing? Do you have different grounds?
@stigigemla
I changed the input.
R17(former R18) I keep, because it makes the amplifier symmetric.
See first post.
I changed the input.
R17(former R18) I keep, because it makes the amplifier symmetric.
See first post.
With 150pF in the Vas I have a problem accepting the last 10KHz square wave in real life.
But then again I was never big on simulations, preferring to build prototypes as I got ideas.
R
But then again I was never big on simulations, preferring to build prototypes as I got ideas.
R
I am pretty sure the amp can do at least 1M unit loop gain bandwidth. The gm of these jfets is very low. You don’t need much Miller cap to compensate it. Something like 47p should be enough. There might be something wrong with your models.
This amp is essentially the Ultra amp with a few minor tweaks. With BD139/139, the miller caps C2/C7 can be eliminated. You'll still have a ULGF of 500kHz and 29db/79 degrees of margin. A healthy stability margin.
However, the design won't work in practice as currently shown in Post #1. I can say this with absolute certainty. The variation of Idss in ACTUAL LSK489/LSJ689 devices is broad. Simulations won't reflect this. You MUST use source resistors (ideally in the form of a trimmer) to allow the JFET currents to be set to a defined level. @mlloyd1, @RM, and @PMA have all expressed the same concern.
In addition, I'm not sure why you have the VAS devices so heavily degenerated. They look to be running around 5mA. 47R should be fine. Performance will likely improve and you'll still have plenty of loop gain margin. You'll seem more improvement if you up the VAS current to 10mA to 12mA.
However, the design won't work in practice as currently shown in Post #1. I can say this with absolute certainty. The variation of Idss in ACTUAL LSK489/LSJ689 devices is broad. Simulations won't reflect this. You MUST use source resistors (ideally in the form of a trimmer) to allow the JFET currents to be set to a defined level. @mlloyd1, @RM, and @PMA have all expressed the same concern.
In addition, I'm not sure why you have the VAS devices so heavily degenerated. They look to be running around 5mA. 47R should be fine. Performance will likely improve and you'll still have plenty of loop gain margin. You'll seem more improvement if you up the VAS current to 10mA to 12mA.
