LSJ177

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Has anyone measured the noise on them? They've been around for a while and frankly for theoretical noise they look better (larger Beta, the transconductance parameter) than the first batch of LSJ74's. The ones given out with Linear Audio were better.

I wrote a little JFET parameter extractor in Python using the Analog Discovery USB data acquisition box. I measure Vgs vs. Id and fit it to the ideal JFET equation. The LSK177 fits almost perfectly, in the picture the measured vs. formula almost lie on top of each other. The red plot is the difference vs Vgs. In general there is a deviation at the low end due to sub-threshold effects (making an accurate direct measurement of Vp almost impossible) and at the high end by the parasitic source resistance.
 

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Fabs matter? Possibly.
I'm in the middle of documenting the construction of some circuitry that won a prize in the 2015 Linear Systems Burning Amp contest (complicated by my main computer system taking a serious dump, but that's another rant).

At any rate, a couple of the circuit modules presented in the contest took advantage of the LS4391, their take on the 2N/PN4391, an erstwhile chopper/switch fet dragooned into service by me as a cascode fet/heavily biased gain amp in a number of my projects.

As a heavily biased class A amp, the Linear Systems take on the 2N/PN4391 displays transconductance more in line with the 2SK/LSK170. (albeit at much higher bias current) than the ORCAD model I have for the 2N/PN4391, causing me to increase the source resistor to tone down the gain of the stage in question. This will be documented when I finally get my main computer back up again and finish the article in question.

Linear Systems was nice enough to send me a generous pile of their 4391 devices as well as the LSK/LSJ parts I won in the contest. They are surprising in that their IDSS is at the low end of the spec in comparison to a lot of the NOS PN4391 parts I have on hand from Fairchild, National, and Siliconix/Vishay. This pleasant surprise makes them more usable in some of my gain cell designs. The extra transconductance was yet another surprise. Noise? Another matter.
 
Fabs matter? Possibly.

As far as our guys think, for PFET's the boron implant is the problem so possibly for switches they have a different process flow (don't know till it's measured). BTW the curve fitting makes a nice matching tool (far better than sorting by Idss) you can match for gm at a given Id (the beta on the LS parts varies more than I thought) or pick source resistors for making current sources without having to trim or select in place. I'm running an experiment now for picking N and P pairs for complimentary output buffers with zero offset. For example N channel no. 1 and P channel no. 16 would bias up at 5mA with a 25.5 Ohm resistor in each source. Simulation shows that doing it this way also is very close to the distortion null.

The beta parameter is also the first line of defense against fakes.

1N Idss = 0.00903431009422 Vp = -0.496867817813 Beta = 0.0365942841949
Resistor for 0.005 A = 25.4456635986
16P Idss = 0.00987679071542 Vp = -0.436152567486 Beta = 0.0519205141692
Resistor for 0.005 A = 25.1656927361
 
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I would not be surprised if the process for the LJS74 is a more critical one than the switches.

> BTW the curve fitting makes a nice matching tool (far better than sorting by Idss) you can match for gm at a given Id (the beta on the LS parts varies more than I thought) or pick source resistors for making current sources without having to trim or select in place.

We have been doing this for years. :)
But to be able to do this, you need to have :

1) equipment to curve trace, curve fit, and compute,
2) a reasonable pool of FETs,
3) knowledge how to use the data to pair,
4) lots of time and patience.

BTW, temperature is also an important parameter to control.
We put the FETs in a specially made oven µP controlled at 30°C, and allow 2 minutes to reach steady state, under bias.


Patrick
 
BTW, temperature is also an important parameter to control.
We put the FETs in a specially made oven µP controlled at 30°C, and allow 2 minutes to reach steady state, under bias.


Patrick

Seems a bit over the top unless extracting bulk Rs and the sub-threshold parameters and doing it over Vds. I have seen batch to batch misfit to the basic Vp, Idss, and lambda equations and then during extended data taking the die temperature is not exactly stationary especially plotting out to high Vds and currents and back. It would be interesting to find the point of diminishing returns. It's not exactly mind focusing effort as grinding a sumi stick before painting.

Nice paper on modeling JFET's not much recent work these days.

FOUR TERMINAL JUNCTION FIELD-EFFECT TRANSISTOR MODEL
FOR COMPUTER-AIDED DESIGN
by
HAO DING
B.S. HuaZhong University of Science & Technology, China
 
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> Seems a bit over the top

There are people who offer matched JFETs claim tomatch to 10µA Idss.
What they don't tell you is that if you just move your head next to the FET, Idss changes more than that.
So the only way for reliable matching over many days is, as we found out, temperature control.


Patrick
 
> Seems a bit over the top

There are people who offer matched JFETs claim tomatch to 10µA Idss.
What they don't tell you is that if you just move your head next to the FET, Idss changes more than that.
So the only way for reliable matching over many days is, as we found out, temperature control.
Patrick

I understand, though the value of 10uA Idss match at exactly one Vds escapes me. Say for instance I wanted Idss and Vp to match one could easily go through a 100 and not find one pair.

BTW if I formed the leads an left the FET's sit in some black foam for a while and then used a tool to grab them and stick them into my socket the results were repeatable to within a few 10's of uA.

That paper was actually his PhD here in Florida, I think it said 2007 later in the title.
 
> Say for instance I wanted Idss and Vp to match one could easily go through a 100 and not find one pair.

You will find more than 1 pair. I am speaking from experience.
We actually match over at the entire curve from Vp to Idss.
And for the Toshiba JFETs at least, the match still largely applies at a different Vds.
(Of course we match at a Vds close enough to the application in the first place.)
For rails >> 15V, we use Cascodes anyway.


Patrick
 
Your yield improves significantly when you go beyond 100~200.
When we match e.g. 1k each, the reject rate is rather low.
For 25 each, you have to have luck.


Patrick

Right like the number of people in a room with the same birthday. I hope you don't take my questions as criticism this level of effort is not for every DIY'er and I don't want folks scared off by the effort and price for discrete design.

I tried out my experiment today out of 25 @ k170/j74 pairs I got 4 that made buffers at 5mA +-1% and < 5mV without a trim and all 8 source resistors one standard 1% value. By chance one pair (the first) was perfect 20uV and 5.001 mA and I thought something was broken.
 
No, not at all. Just pointing out facts.

A BL grade starts at 6mA and ends at 11mA.
So you can image a uniform spread with 25 devices and the average difference would be 0.2mA.
You would have to have luck to come below 1%.

But unless one is using complementary pairs for even harmonic cancellation, perfect pairing (curve match) is not so important.

They are not so easy to get anymore anyhow.
And those on offer are more often than not already matched.


Patrick
 
No, not at all. Just pointing out facts.

A BL grade starts at 6mA and ends at 11mA.
So you can image a uniform spread with 25 devices and the average difference would be 0.2mA.
You would have to have luck to come below 1%.

But unless one is using complementary pairs for even harmonic cancellation, perfect pairing (curve match) is not so important.

They are not so easy to get anymore anyhow.
And those on offer are more often than not already matched.


Patrick

Right my headspace, a simple statistics problem.
 
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