Originally posted by millwood
I think yes.
Paralleled inductances follow the equation:
1/Ltotal = 1/L1 + 1/L2 + 1/L3………………
Greetings
KlausB
really? you can reduce inductance by paralleling them?
I think yes.

Paralleled inductances follow the equation:
1/Ltotal = 1/L1 + 1/L2 + 1/L3………………
Greetings
KlausB
Throw the white towel and use both methods.
Parallel caps, one near each output transistor,
plus the large cans on the power supply
Parallel caps, one near each output transistor,
plus the large cans on the power supply

Parallel caps, one near each output transistor,
Nice idea! But only if it will fit my enclosure.
JojoD
Hi,
Just don't forget that by //ing multiple caps you're bound to augment the used surface area which in turn will augment ESL...
In a pretty much unpredictable way.....
Cheers,😉
Just don't forget that by //ing multiple caps you're bound to augment the used surface area which in turn will augment ESL...
In a pretty much unpredictable way.....
Cheers,😉
The increase in surface area might help to run them cooler, and in turn increase lifetime.
And it seems that the ripple current that many parallel caps can bear is indeed larger than that of a single one.
Example Evox RIFA PEH 169 / 63 V @ 105 deg & 100 Hz:
2200 uF : 4.1 A
10000 uF : 9.9 A
Regards
Charles
And it seems that the ripple current that many parallel caps can bear is indeed larger than that of a single one.
Example Evox RIFA PEH 169 / 63 V @ 105 deg & 100 Hz:
2200 uF : 4.1 A
10000 uF : 9.9 A
Regards
Charles
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