Looking for someone to collaborate on DAC design

[Terry Demol]

Koinichiwa,

The smallest step of programmable clock divided by two determines the maximum deviation between the clocks once "lock" is achieved. The AD9850 has an output tuning resolution of 0.0291Hz.

If we take a CD "retime" master clock of 11.2896MHz and have a FIFO buffer set (wee need three to make that easy to work - thanX to the other Guido for that hint) of the shortest type (256bit each) and aim to allways keep the middle buffer changing between full and empty we should have no activity in the controller once locked for hours at a time.

Yes, such a system will be relatively slow to settle to a full lock, but if we have it on for a while it MUST tend to a minimum deviation. I suspect that simply pre-setting the clock from the input frequency information from the DIR Chip will be enough to keep the first clock change down to a few seconds away.

So an anlogy to the function of a PLL exists but due to the digital nature of the system it is possible to settle to an absolute steady state with no activity.



Sure. But our clock pulse jumps (theoretically) are at 0.0291Hz out of 11.2896 MHz or 0.0026 PPM.

As for Guido's pulled VCXO, to cover 44.1KHz, 48KHz, 88.1KHz, 96KHz, 176KHz and 192KHz sample rates you ned an awfull lot of circuitry.

And all these frequencies may be encountered at some time from the Digital out of a universal DVD Video/Audio Player, depending if you play a DVD Movie, a CD or an Audio DVD. Hance my thought that all these Frequencies must be transparently handeled. And this of course is also the need for the Memory buffer as the clock in these things is positively dibolical.

The downside of this implementation is that it is a little past "kitchen table" electronics, but implemented well and sold as assebled module I suspect you would pick up both OEM's to incorporate this in their gear and it would eb an easy upgrade. Done in SMD the whole board can be tiny.

Sayonara

G'day Kuei (T),

A few manufacturers are using similar concepts.
dB Technologies and Weiss are using FIFO based jitter
attenuators. Weiss has sub 1Hz ut uses VCXO with very
tight pull range for low phase noise.

You might want to talk to David Broadhurst as he is also
developing such a system based on AD9850.

http://www.geocities.com/capecanaveral/galaxy/6623/buffer.html

AFAIK AD9850 doesn't equal a really good VCXO's phase noise
peformance but maybe that's not the limiting factor....

What are master Guido Tents views on this?

Terry

 

[Pjotr]

Pjotr:

Your configuration sounds like a delay-locked loop (DLL). While not as common as PLLs, there is considerable literature on them. IIRC, it is easier to get low jitter out of a DLL than out of a PLL. Their main drawback is that they cannot be used for arbitrary (M/N) frequency synthesis, but are limited to integer multiples of the reference clock. Since you are not multiplying the clock, this is not an issue.

Hi Mike,

It is in fact a PLL. Using my proposed approach will give a phase detector with a much wider phase range. Using 8 bit counters will give a phase detector with a range of ± 256 x phi. To accommodate that concerning the audio data you need shift registers or a dual ported RAM. The corner frequency of the loop filter can be very low then (under 1 Hz) without a very long lock-in time.

Btw. K.Y.W. how is your collaborating DAC project going?


😎

 

[mikewu99]

It is in fact a PLL.

Upon closer reading of your original description I agree.

I am thinking of a similar configuration, except that instead of adjusting the DAC clock to match the transport I would adjust the transport clock to match the DAC clock, thereby ensuring tha DAC clock is the lowest jitter clock in the system. I had thought of modifying a cheapo CD player with S/PDIF output to use as a transport if I could find one where a single clock controls the data rate. I would modify the CD player to accept the control signal from the PLL (either digital or analog feedback). Since I no longer care about interface jitter but only bit-error rate, I could use the existing optical S/PDIF connection to get good electrical isolation between transport and DAC. I could use a second S/PDIF-type interface running in the reverse direction to send the PLL control signal to the CD player/transport.

Actually, if I could figure out how to interface to a USB CD-ROM drive that might be even easier - set it up to transfer a burst of data when my FIFO get low. The modified CD player as transport would probably have a better user interface, though.

When I would have time to do all this is another question - I need to get some other non-audio projects done before I could get SWMBO approval...

 

[Pjotr]

Mike, the Philips CDP-Pro transport uses a single clock oscillator. But have look at the whole thing.

First of all, the nasty influence of jitter has the most impact on the higher signal frequencies, the mid and top range of the sound. It generates side bands on a single tone for instance and as such "blurring" it.

Second the side band noise of an X-tal oscillator is limited to the quality of the crystal, or in other words the band pass filtering capabilities of the crystal. The better it is, the smaller the side band noise can be. And of course the noise of the amplifying transistor used in the oscillator plays its role.

If we could manage a jitter-free VCO, then a PLL acts as a 12dB/okt low pass filter for the jitter of the incoming clock signal that has to be recovered. So if the corner frequency of the closed loop response of the PLL is 1Hz, incoming jitter at 10 Hz is attenuated by 40 dB and at 100Hz by 80 dB, roughly speaking. A 11 MHz X-tal oscillator with a smaller sideband noise bandwith than 10 Hz is really a very good one.

The jitter of the Crystal receiver chips is specified at 800 ps_pp. The best commercial HCMOS VCXO’s have a specified jtter of 20 ps_pp or 5 ps_rms. There are better ones but these are PECL VCXO’s. The bandwidth of the jitter is not given so I assume it is wide band. So if we attenuate the incoming jitter by 800/20 = 40 times we are on the performance of the X-tal oscillator itself.

IMHO a PLL with a closed-loop corner frequency of 1 Hz will do the job quite well. Lower corner frequencies or a transport locked to the DAC will do no better and make no sense compared to a well-laid out external DAC that is locked to the transport IMHO. Technically realising it is another story 😉

Regards