Hi,
I bought a QCC3031 "HY1002" bluetooth module (https://www.aliexpress.us/item/3256805281764019.html?gatewayAdapt=glo2usa4itemAdapt) that I am trying to use in a Kef X300A powered speaker.
The X300A has an analog "line in" input that is routed to a WM8782A ADC setup in slave mode. My plan was to replace the ADC with Bluetooth module. I got it to produce garbled sound via I2s. My issue seems to be clock timings for i2s. I need to emulate the configuration currently setup for the WM8782A. I loaded the Qualcomm ADK configuration tool for this purpose. I got the module up on the config tool via USB. The WM8782A is configured for the following.
WM8782A Config
-Slave mode, 128,192,256,384,512,768fs
-24 bit word length
-96khz fast sample rate
-audio mode I2s
When the WM8782A was in circuit I got MCLK = 24MHZ, BCLK=6MHZ and LRCLK=96KHZ.
My question is, can I get the QCC3031 to emulate the WM8782A using the Qualcomm ADK configuration tool? Unfortunately, I am out of my league when it comes to i2S programming. I see that an .xml file for configuration can be loaded. Does anyone have a configuration file that might work? I have schematics and info for both the X300A and the QCC3031 module.
Any help would be appreciated.
Gary
I bought a QCC3031 "HY1002" bluetooth module (https://www.aliexpress.us/item/3256805281764019.html?gatewayAdapt=glo2usa4itemAdapt) that I am trying to use in a Kef X300A powered speaker.
The X300A has an analog "line in" input that is routed to a WM8782A ADC setup in slave mode. My plan was to replace the ADC with Bluetooth module. I got it to produce garbled sound via I2s. My issue seems to be clock timings for i2s. I need to emulate the configuration currently setup for the WM8782A. I loaded the Qualcomm ADK configuration tool for this purpose. I got the module up on the config tool via USB. The WM8782A is configured for the following.
WM8782A Config
-Slave mode, 128,192,256,384,512,768fs
-24 bit word length
-96khz fast sample rate
-audio mode I2s
When the WM8782A was in circuit I got MCLK = 24MHZ, BCLK=6MHZ and LRCLK=96KHZ.
My question is, can I get the QCC3031 to emulate the WM8782A using the Qualcomm ADK configuration tool? Unfortunately, I am out of my league when it comes to i2S programming. I see that an .xml file for configuration can be loaded. Does anyone have a configuration file that might work? I have schematics and info for both the X300A and the QCC3031 module.
Any help would be appreciated.
Gary
@gmaff I am not well-versed with I2S myself, but if you share the dump file from your QCC3031, I can take a look at it and see if I can help with the configuration. I’m not sure how familiar you are with the ADK Config. Tool, but I’ll explain how to get the dump file just in case.
Assuming you’ve already established a connection to the module with ADK Config. Tool, select “Go Configurable” then select “Read Device.” Lastly, select “Save ConfigSet Dump File.”
Post .xml file here and maybe I can help or someone else can offer more input on the topic of I2S.
Assuming you’ve already established a connection to the module with ADK Config. Tool, select “Go Configurable” then select “Read Device.” Lastly, select “Save ConfigSet Dump File.”
Post .xml file here and maybe I can help or someone else can offer more input on the topic of I2S.
Hi Gary,
Fascinating project. I guess my only question would be whether you have the module accepting MCLK/BCLK from the X300A, rather than generating them itself.
MCLK is a high-speed reference clock, and seems to be 256fs (i.e. 256 * 96k = 24.576MHz)
BCLK is the serial bit clock, and seems to be 32 bits * 2 channels * 96k = 6.144MHz.
If you're getting some garbled audio, it's almost as though your clocks are correct (+/- epsilon) but in the wrong direction (i.e. master, and therefore not synced to the X300A's I2S bus)? Again, if you were to post your XML config file, maybe that would give us some hints...
Fascinating project. I guess my only question would be whether you have the module accepting MCLK/BCLK from the X300A, rather than generating them itself.
MCLK is a high-speed reference clock, and seems to be 256fs (i.e. 256 * 96k = 24.576MHz)
BCLK is the serial bit clock, and seems to be 32 bits * 2 channels * 96k = 6.144MHz.
If you're getting some garbled audio, it's almost as though your clocks are correct (+/- epsilon) but in the wrong direction (i.e. master, and therefore not synced to the X300A's I2S bus)? Again, if you were to post your XML config file, maybe that would give us some hints...
Hi, I know its been a long time but I am looking at this today. I bought another exact same module configured for I2s. I got nothing out of it until I changed Master/Slave to Slave. See attached Dumpfile. I now get the same garbled audio I had with the other Dumpfile