Rüdiger,
you have to tight collectors of input pair at higher voltages than you do.
CCS + diode bias related to output would make it.
you have to tight collectors of input pair at higher voltages than you do.
CCS + diode bias related to output would make it.
Rudy,
Have you tried base stoppers of 47R on the drivers, and 10R on the outputs, and perhaps if you introduce emitter degeneration on the outputs, also 10R, whilst keeping the output in Class A as PMA suggests.
This approach is resistive and benign, rather than strapping in capacitive manacles which slows it all down.
The problem with oscillation could be periodic episodes of negative input impedance at the base of the outputs......
Excessive local FB around the output CFP might be exacerbating this.
Otherwise it's a very elegant circuit and clearly has the potential for outstanding numbers,
Cheers,
Hugh
Have you tried base stoppers of 47R on the drivers, and 10R on the outputs, and perhaps if you introduce emitter degeneration on the outputs, also 10R, whilst keeping the output in Class A as PMA suggests.
This approach is resistive and benign, rather than strapping in capacitive manacles which slows it all down.
The problem with oscillation could be periodic episodes of negative input impedance at the base of the outputs......
Excessive local FB around the output CFP might be exacerbating this.
Otherwise it's a very elegant circuit and clearly has the potential for outstanding numbers,
Cheers,
Hugh
@Pavel:
Well, pseudo-Darlingtons using complementaries, thas is... just a matter of definition, my textbook (Tietze/Schenk) calls that a darlington, here it is known as CFP.
@Hugh:
I think the "cascoding trick" is just the speciality of this circuit, but it doesn't seem to be essential for the performance. When we break the feedback, hooking the input collectors to the supplies, everything is fine, but distortion is a bit higher.
EDIT: output degen. helped... but with high values (~100R) which would increase ouput impedance.
@Rüdiger:
The loop-gain probing is a bit difficult in this setup, so I tried the normal approach looking at the step response. I ended up with degenerating the feedback for high frequencies, by dividing down the AC at the collectors. This comes at the cost of lesser cascoding voltage.
See attached test. It can be seen it is quite stable (though not pefectly damped) with any source R from 10R to 10k, but with higher source impedance more DC-offset is introduced, also distortion "goes up" from 0.6ppm to 0.11ppm ;-)
- Klaus
Well, pseudo-Darlingtons using complementaries, thas is... just a matter of definition, my textbook (Tietze/Schenk) calls that a darlington, here it is known as CFP.
@Hugh:
I think the "cascoding trick" is just the speciality of this circuit, but it doesn't seem to be essential for the performance. When we break the feedback, hooking the input collectors to the supplies, everything is fine, but distortion is a bit higher.
EDIT: output degen. helped... but with high values (~100R) which would increase ouput impedance.
@Rüdiger:
The loop-gain probing is a bit difficult in this setup, so I tried the normal approach looking at the step response. I ended up with degenerating the feedback for high frequencies, by dividing down the AC at the collectors. This comes at the cost of lesser cascoding voltage.
See attached test. It can be seen it is quite stable (though not pefectly damped) with any source R from 10R to 10k, but with higher source impedance more DC-offset is introduced, also distortion "goes up" from 0.6ppm to 0.11ppm ;-)
- Klaus
Attachments
Thanks so far for all your suggestions -- it's nice being close to something and being backed by you!
Pavel, yes, the misbehaviour goes along with a slight de-tune of circuit balance when the input is forced to or near ground.
I did, however, not get what you have in mind with the CCS related to the output.
I'll try with the other suggestions since.
Rüdiger
Pavel, yes, the misbehaviour goes along with a slight de-tune of circuit balance when the input is forced to or near ground.
I did, however, not get what you have in mind with the CCS related to the output.
I'll try with the other suggestions since.
Rüdiger
I think what Pavel means is to raise the input's Vce by one diode drop (currently it's ~1.2V), which could be had by connecting diodes to the output's emitters and forward bias them with a CCS from the corresponding supplies.
- Klaus
- Klaus
Well, I guess, there's no quick shot possible.
Since we have to break the short link between the input collectors and the emitter nodes of the compound pair, we fall somewhat back with the 50k/50k divider (0.000020%), with 99.99k/10 we settle at [Edit] 0.0002%.
Step response won't be perfect still, but better.
For comparison: while the curl follower (CCS'ed jfet follower out of a single 2SK389) sims at 0.0054% at 1V (10k load), it sims with 0.000015% at this attenuator setting, this time with 500R load. (0.000001% with 10k)
So, I will try the other suggestions as well and see where it gets me.
Rüdiger
Since we have to break the short link between the input collectors and the emitter nodes of the compound pair, we fall somewhat back with the 50k/50k divider (0.000020%), with 99.99k/10 we settle at [Edit] 0.0002%.
Step response won't be perfect still, but better.
For comparison: while the curl follower (CCS'ed jfet follower out of a single 2SK389) sims at 0.0054% at 1V (10k load), it sims with 0.000015% at this attenuator setting, this time with 500R load. (0.000001% with 10k)
So, I will try the other suggestions as well and see where it gets me.
Rüdiger
I do not think that 0.0000X% or 0.0000Y% really matters. I am quite sure that stability is an ultimate requirement. For this reason, I tight collectors of an input complementary pair to supply rails, though distortion is a bit higher then, due to Early effect.
PMA said:
When we talk sound quality I agree that stability is the utmost demand, and those numbers are something else. Still, who knows, where it gets me.
Rüdiger
When I look a little closer at the circuit, I find that then one looses the additional current sinking through the input trannies; that is, there is no option for a current polarity change in the output emitter R's. With the original hookup, the additional +-10mA from the CCS's are available to maintain class A.PMA said:
Of course stability is a big concern... in this case also ferrite bead in the inputs might be worth a try...
- Klaus
I didn't know that this old buffer design from tube age now is called the "Curl follower". A modern reference is given in the Siliconix AppNote 102, JFET Biasing Techniques.Onvinyl said:
- Klaus
Klaus, now I'm confused.
What is the 'original'? Post #1? The input T's as CCS for the output is my post #2, with the input collectors tied to the emitter nodes of the compound pair.
The stability concerns are with both versions. The version #1 exists in reality on my perfboard and has issues with low resistance to ground (low volume pot setting) at the input that is reflected well in the simulation with LTSPice. Even the oscillating frequency is close. With higher settings, the circuits behaviour is good.
The stability concerns with the version of post #2 are more severe, according to sim. I haven't build it so far, I will, if I find out why exactly it's oscillating.
re follower: there were some extensive discussions around several of those simple followers some years ago here. The sound of this particulary one I'm using now is not easy to beat, and it has low DC-offset for free.
Rüdiger
EDIT: 'Sound' read 'transparency'
What is the 'original'? Post #1? The input T's as CCS for the output is my post #2, with the input collectors tied to the emitter nodes of the compound pair.
The stability concerns are with both versions. The version #1 exists in reality on my perfboard and has issues with low resistance to ground (low volume pot setting) at the input that is reflected well in the simulation with LTSPice. Even the oscillating frequency is close. With higher settings, the circuits behaviour is good.
The stability concerns with the version of post #2 are more severe, according to sim. I haven't build it so far, I will, if I find out why exactly it's oscillating.
re follower: there were some extensive discussions around several of those simple followers some years ago here. The sound of this particulary one I'm using now is not easy to beat, and it has low DC-offset for free.
Rüdiger
EDIT: 'Sound' read 'transparency'
Rüdi, I meant #2. #1 is stable in my sim with any R_src, even with no output load and high supply impedance. Must be the different trannies... I might try the BCxxx models from the Philips library (Orcad, phil_bjt.lib) to see what happens. What were the models you used, and can you post them?
- Klaus
- Klaus
Klaus,
fairchild, obviously. I googled them somewhere.
Meanwhile, I tried your scheme, and things get a lot worse, so I'm confident that different transistors play a major role here.
I don't know how they come out here:
.model BC560 pnp
+ IS = 5.11839E-13 BF = 200.0 NF = 1.00811
+ BR = 0.66 NR = 1 ISE = 1.32082E-12
+ NE = 1.5 ISC = 5.24807E-12 NC = 2
+ VAF = 211.586 VAR = 20 IKF = 0.0448
+ IKR = 1.31826E-4 RB = 200 RBM = 0.496
+ IRB = 1.584893E-5 RE = 6.09 RC = 8.05
+ CJC = 9.014673E-12 VJC = 0.3068755 MJC = 0.3580011
+ TF = 1.06e-9
* -------------------------------------------------------------------
* Creation: Mar-7-2005
* Fairchild Semiconductor
.MODEL BC549/550 NPN
+ LEVEL = 1
+ IS = 2.24183E-14
+ NF = 0.996496
+ ISE = 1.90217E-14
+ NE = 2
+ BF = 228.4
+ IKF = 0.211766
+ VAF = 161.939
+ NR = 0.993
+ ISC = 4.7863E-15
+ NC = 0.996
+ BR = 12.1807
+ IKR = 0.3423
+ VAR = 123.229
+ RB = 167.033
+ IRB = 7.079458E-05
+ RBM = 1.12256
+ RE = 0.036
+ RC = 0.79
+ XTB = 1.65
+ EG = 1.1737
+ XTI = 3
+ CJE = 1.87E-11
+ VJE = 0.732
+ MJE = 0.33
+ CJC = 6.16E-12
+ VJC = 0.395
+ MJC = 0.251
+ XCJC = 0.6192
+ FC = 0.5
+ TF = 518.15E-12
+ XTF = 10
+ VTF = 10
+ ITF = 1
+ TR = 10.000E-9
* -------------------------------------------------------------------
* FAIRCHILD CASE: TO-92 PID: BC549/550
* APR-12-2001 CREATION
fairchild, obviously. I googled them somewhere.
Meanwhile, I tried your scheme, and things get a lot worse, so I'm confident that different transistors play a major role here.
I don't know how they come out here:
.model BC560 pnp
+ IS = 5.11839E-13 BF = 200.0 NF = 1.00811
+ BR = 0.66 NR = 1 ISE = 1.32082E-12
+ NE = 1.5 ISC = 5.24807E-12 NC = 2
+ VAF = 211.586 VAR = 20 IKF = 0.0448
+ IKR = 1.31826E-4 RB = 200 RBM = 0.496
+ IRB = 1.584893E-5 RE = 6.09 RC = 8.05
+ CJC = 9.014673E-12 VJC = 0.3068755 MJC = 0.3580011
+ TF = 1.06e-9
* -------------------------------------------------------------------
* Creation: Mar-7-2005
* Fairchild Semiconductor
.MODEL BC549/550 NPN
+ LEVEL = 1
+ IS = 2.24183E-14
+ NF = 0.996496
+ ISE = 1.90217E-14
+ NE = 2
+ BF = 228.4
+ IKF = 0.211766
+ VAF = 161.939
+ NR = 0.993
+ ISC = 4.7863E-15
+ NC = 0.996
+ BR = 12.1807
+ IKR = 0.3423
+ VAR = 123.229
+ RB = 167.033
+ IRB = 7.079458E-05
+ RBM = 1.12256
+ RE = 0.036
+ RC = 0.79
+ XTB = 1.65
+ EG = 1.1737
+ XTI = 3
+ CJE = 1.87E-11
+ VJE = 0.732
+ MJE = 0.33
+ CJC = 6.16E-12
+ VJC = 0.395
+ MJC = 0.251
+ XCJC = 0.6192
+ FC = 0.5
+ TF = 518.15E-12
+ XTF = 10
+ VTF = 10
+ ITF = 1
+ TR = 10.000E-9
* -------------------------------------------------------------------
* FAIRCHILD CASE: TO-92 PID: BC549/550
* APR-12-2001 CREATION
Rüdiger,
I've tried it with your models, but no change:
- circuit #1 is stable**)
- circuit #2 is unstable below ~500Ohms
- compensated #2 is stable**)
**) but with decreasing margin at lower source impedances, step response (also of the internal currents) looks very well down to ~1k, no significant overshoot.
I didn't sim the supply details, maybe the problem comes from that?...
- Klaus
I've tried it with your models, but no change:
- circuit #1 is stable**)
- circuit #2 is unstable below ~500Ohms
- compensated #2 is stable**)
**) but with decreasing margin at lower source impedances, step response (also of the internal currents) looks very well down to ~1k, no significant overshoot.
I didn't sim the supply details, maybe the problem comes from that?...
- Klaus
Hi Klaus,
with your parts, #2 is more tame. But you lose the advantages over #1 as well---
it's true, #1 is stable without shunt regs. So an additional issue is to update the regulator (since I have no ideal voltage source handy)...
I find it disturbing, however, that with a ratio below 99k/1k the distortion start to rise (it decreases with smaller amplitude just as it should with more even ratios).
That leads to another question: how is the situation with a high Z output stage (VAS, folded cascode...) Are there situations where the dynamic impedance is effectivly lower, so low that it would disturb the circuit?
Rüdiger
with your parts, #2 is more tame. But you lose the advantages over #1 as well---
it's true, #1 is stable without shunt regs. So an additional issue is to update the regulator (since I have no ideal voltage source handy)...
I find it disturbing, however, that with a ratio below 99k/1k the distortion start to rise (it decreases with smaller amplitude just as it should with more even ratios).
That leads to another question: how is the situation with a high Z output stage (VAS, folded cascode...) Are there situations where the dynamic impedance is effectivly lower, so low that it would disturb the circuit?
Rüdiger
Sorry in advance for the distraction, but I've never used the .four in LTSpice. I always seem to get a bit less than .1%, even if I look right at the voltage source. Has to be something really dumb like sample length or something. What might I be doing wrong?
Conrad Hoffman said:
Have you disabled compression in Tols->Control panel (all three of them)? You have to do that every time you start LTSwCad, or place .option plotwinsize=0 as spice directive on every sch you try to sim.
Conrad,
it would be nice if you could keep this thread on topic. It happens, that I had the same question last week, though:
spice for beginners
Rüdiger
it would be nice if you could keep this thread on topic. It happens, that I had the same question last week, though:
spice for beginners
Rüdiger
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