john curl said:
Most simulators these days come with high tech plastic cases and don't make very good heatsinks.
Well, DOUBLE DUH, to you, Scott! Tell me something that I don't know, like the peak beta of your NPN output transistor in your AD797.
We seem to be off target, but actually real understanding can be gained from the recent inputs to this thread.
First, 100% simulation, can be more trouble than it first appears to be.
Sooner, or later, you have to get your feet wet and actually build a real prototype.
This is especially true with discrete designs, as the transistor models are only so-so, and not as perfect as the models IC users use for their devices, in house.
Another factor is actually trying a heatsink, often made by someone else, and seeing how well it really works. An infrared temp sensor is best for this. It is fast, and easy. For the JC-1, the devices are laid out at the same height in parallel and equidistant from each other for the most part. This really helps to keep thermal runaway from happening.
Some simulator, somewhere, I'm sure, can do thermal analysis of heatsinks, but I have never had access to one. Has anyone on this thread?
First, 100% simulation, can be more trouble than it first appears to be.
Sooner, or later, you have to get your feet wet and actually build a real prototype.
This is especially true with discrete designs, as the transistor models are only so-so, and not as perfect as the models IC users use for their devices, in house.
Another factor is actually trying a heatsink, often made by someone else, and seeing how well it really works. An infrared temp sensor is best for this. It is fast, and easy. For the JC-1, the devices are laid out at the same height in parallel and equidistant from each other for the most part. This really helps to keep thermal runaway from happening.
Some simulator, somewhere, I'm sure, can do thermal analysis of heatsinks, but I have never had access to one. Has anyone on this thread?
john curl said:
For temperature rise, it is helpfull to view a heatsing as having a thermal resistance to ambient, and the devices as thermal (voltage or current) generators. Then, if you want each device on the heatsink to have the same temp rise, each 'generator' must see the same equivalent termination. That turns the heasink and its devices into a matrix of generators and load impedances and the task is then to physically arrange them in such a way that they all get the same temp rise.
It is very unlikely that equidistant arrangements give the same temp rise. The closer you get with the devices to the center of the sink, the more space you want between adjacent devices.
There *are* some things you can figure out without building a sample and even without simming 😉
Jan Didden
I think orcad Pspice can do it.. I tried the 'smoke" plugin that
came with it and it allowed a C/watt entry .. but it said that
my device model was missing certain parameters.
After looking up WHAT parameters were missing in the LT
manual, I found that many of my fairchild/ ON BJT models
omitted the necessary parameters.
A lot more FET's seem to have this thermal data, so I just
finalize the "doable" design aspects and leave the Tcomp
to the real world. I might take an hour to do on the real amp,
but to set up LT or orcad to model both the device and the heatsink (big learning curve) faithfully ,one could compensate
(trial and error)several amps in the real world. 🙁
OS
janneman said:
Fact remains, that it would take a very complicated model, to simulate the working parameters for a heatsink.
A few parameters that are usually not taken into account, but happens to make a whole lot of difference to a passive heatsink:
Distance from floor/shelf to bottom of heatsink.
Direction of air "intake", by this I mean is the amp on a shelf up against a wall, or standing in free air on all sides.
Draught around the amp.
Once the thermal demands gets high, these factors will have a lot of influence, especially on big heatsinks with skimpy back-bones.
A real world test, in situ, is AFAIK the only feasible solution for one off's as most of us builds.
Magura 🙂
One way to get around the whole issue, is to use a hefty heat-spreader, preferably made of either carbon or copper.
The thermal transfer capabilities of these materials, pretty much deals with the issue.
Carbon works a bit better than copper in this aspect.
Magura 🙂
The thermal transfer capabilities of these materials, pretty much deals with the issue.
Carbon works a bit better than copper in this aspect.
Magura 🙂
I think 16x TO-247 or 264 devices bolted onto a 0.3 deg C/W heatsink should run pretty much within a degree or two of each other - of course, assuming these ar e matched device s and Re is are also decent types and matched within a few percent.
Of course, if you are bolting these to a 5 deg C/W heatsink, devices are not matched, Re are 10% types then you deserve to get problems
Of course, if you are bolting these to a 5 deg C/W heatsink, devices are not matched, Re are 10% types then you deserve to get problems
Yes, there are many other factors involved, but my point was that putting them equidistant from each other as John went through efforts to do that, by definition does NOT give them equal temperatures.
Your heatsing is hottest in the center and cooler towards the end if you heat it with equidistantly mounted devices. To keep the temp uniform, you place more heat generators toward the outside and more space betweeen them towards the center.
Jan Didden
Your heatsing is hottest in the center and cooler towards the end if you heat it with equidistantly mounted devices. To keep the temp uniform, you place more heat generators toward the outside and more space betweeen them towards the center.
Jan Didden
with simple layout using equal power devices, one can notionally "divide" up the heatsink into equal "areas" and place one device in the centre of each area.
Two devices would be at 25% and 75% from one side.
Three devices would be located at 16% and 50% and 84% from one side.
Four devices would be located at 12%, 37%, 63% and 88% from one side.
The closer that the backplate gets to isothermal the closer it approaches the manufacturer's claimed Rh s-a.
Two devices would be at 25% and 75% from one side.
Three devices would be located at 16% and 50% and 84% from one side.
Four devices would be located at 12%, 37%, 63% and 88% from one side.
The closer that the backplate gets to isothermal the closer it approaches the manufacturer's claimed Rh s-a.
janneman said:
If you want to calculate by hand cooling problems including conduction, radiation, convection forced and natural I strongly suggest the reading of:
Cooling techniques for electronic equipment by Dave Steinberg.
This is a book that allows you to calculate all the practical configurations. It gives you the practical and simple equations to use and the practical simplifications to study real cases.
There is no derivations of the basic equations but better an expanation how to use them in the real world.
For example, you will be able to calculate fan cooled electronic boxes using convection coefficients calculated for the actual geometry of your boxe using Colburn factor, Reynolds number given for all practical shapes. Easy to read and understand without having to dig in complex litterature.
Even if you use thermal models and computer methods you will need these skills to understand how to design, improve and to understand if your simulation is correct ( same as Spice).
JPV
a dilemma?
From a electrical point of view, i.e. for minimum lead or trace inductance, it's better to put the O/P trannies as close as possible together.
From a electrical point of view, i.e. for minimum lead or trace inductance, it's better to put the O/P trannies as close as possible together.
john curl said:
That process is basicly in the "no new designs" phase I could probably send you a beta vs. Ic plot if I could find one.
jacco vermeulen said:
Nice reference. For those who haven't loopked. this is a full free book pdf file with coverage of much to do with "packaging" of electronics and includes good work on military and avionics equipment that just as easily applies here.
Well, we are going to use your AD797 anyway. Thanks for the response on the Beta peak. When I design things I KNOW where the peak beta is in my head, because I memorize it. This is what confuses the guys trying to make the Levinson JC-2 modules, as they don't know why I chose and biased the output transistors the way that I did. I used to virtually memorize the spec sheets.
john curl said:
Just curious John, how would knowing the beta peak of the NPN output transistor in AD797 help you designing a better application?
- Status
- Not open for further replies.