Okay, found this complete version, Ben van Oosten "Organ Symphony No 6" Widor - YouTube, available in HD. Sorry, the Adagio doesn't do it for me, but the first and last movements have got plenty of oomph, and bite - might do a recording of playback of one of those ...
-The 170dc weighs 30lb total. A decent 600/625VA toroidal clocks in at 10/11lb, an equivalent size EI weighs a whole lot more than that.
-a clear indication for VA rating is the core size, a 600VA EI requires a decent size.
-fuse amp rating is an indication, not absolution.
There are various freebee download tutorials on how to design laminated transformers, which include picking a core size and weight estimates.
(learn how to build yachts/ships, and it comes as a gratuity. Oh Dear, that's engineering)
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Why you choose to make that obscure point is beyond me. The whole point of this exercise was the semi-confidential admission by a semi vendor that they sort by test.
Having DONE so personally at the wafer level and at the final component level for the largest diode manufacturer in the world, I personally attested to that fact as per experience.
You suddenly coming in and claiming that it does not happen because of the "billions and billions " of parts your employer makes does not change reality.
And to your statement. I have NEVER claimed that everybody regardless of volume tests by sort or by branch, so have never compared high and low volume.
What is "*******" me off is your use of strawman arguments and ill informed statements about what I've stated.
Stop.
jn
Try this one, Frank:
https://www.dropbox.com/s/caykyurgjlm0wrv/sample.wav
Much better quality. Not joking. Complete DIY.
Hi and sorry but i had to try 🙂
No seriously ... so many OT i have never seen really
The Lounge is fine ... the title should be revised i think.
If i understand it is a sort of annoying attempt to make the designer to disclose the circuit ? 🙄
I agree 😉
Regards, gino 😀
Quote "A good high volume fab line can trivially exceed wafer probe testing by orders of magnitude. "
This is exactly the point I've been trying to explain - you cannot work like this today on high volume lines. Period.
Quote "However, to blindly assert that every fab line on the planet for every semiconductor process doesn't test and sort is utter nonsense."
I do not recall making a blanket statement like that. We were talking about high volume devices and the context was discretes.
I rest my case.
George, it is not required to reduce sag (! LOL), it is required to introduce (analog) tape delay when cutting records. Take a closer look at that picture and diagram in upper left corner of the headblock. See the various loops at various tape speeds and various lathe revolutions? First head reads material and adjusts lathe pitch etc., second head drives the cutter.
In the '80s many records were cut with regular machines where delayed signal came from digital delay (AD->delay->DA). What do you say now, you vinyl fetischists?
This is how complete pre-listen machines looks like. 1/2 inch, 1 inch and 1/4 inch.
Best,
Attachments
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I have question about biasing Jfets beyond there IDSS current - that is, for example, taking the gate of an N channel Jfet more positive than the source.
I remember that Nelson stated a while back that Jets really "sing" when they are run close to their IDSS current.
In Spice I notice that the current increases towards and past the IDSS value as the voltage is raised on the gate however in data sheets & books I cannot find any reference to this mode of operation.
If I set the operating point of a Jfet precisely at it's IDSS, when a signal is added there will be times when:
1) The current exceeds the stated IDSS current.
2) The gate is more positive than the source.
In a practical circuit tested in spice I noticed that the gate voltage peaked at about 15mV above the source.
Given that I am with the stated power limits of the device, is there any inherent danger to the component in running it in this way or, should I bias the Jfet so the entire signal swing stays at or below IDSS.
thanks
mike
I remember that Nelson stated a while back that Jets really "sing" when they are run close to their IDSS current.
In Spice I notice that the current increases towards and past the IDSS value as the voltage is raised on the gate however in data sheets & books I cannot find any reference to this mode of operation.
If I set the operating point of a Jfet precisely at it's IDSS, when a signal is added there will be times when:
1) The current exceeds the stated IDSS current.
2) The gate is more positive than the source.
In a practical circuit tested in spice I noticed that the gate voltage peaked at about 15mV above the source.
Given that I am with the stated power limits of the device, is there any inherent danger to the component in running it in this way or, should I bias the Jfet so the entire signal swing stays at or below IDSS.
thanks
mike
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They work fine up to even .2 or .3 V forward gate voltage, you just don't want any gate current because then things get pretty non-linear and this happens by .5 or .6V. A typical diode check on a multimeter will give the diode voltage at 100uA or so, you can just use the diode equation to see where the forward current is more than 10's of pA.
Actually, if you have 110Hz and 165Hz your mind will create the 55Hz, as
the missing part of a natural harmonic series .
Missing fundamental - Wikipedia, the free encyclopedia
So you're saying Franky has pcp level imagination, hence the greatness from his PC speakers ...🙂
Hmmm.. You quote me, and then state that you are arguing the point?? If I say the earth is round, will you quote that as well and then argue that the earth is round??
You introduced high volume to explain why semi manu's don't sort. You are incorrect. And descretes as an argument also fails.
In point of fact, it is impossible to test at the wafer level any device which is passivated at a subsequent process test. In other words, every single solitary axial lead diode made on this planet (there are a few minor exceptions that I will not go into) MUST be sorted by test for leakage and breakdown. NEVER can that be done at the wafer level. My previous employ shipped 11 million diodes per day (20 years ago), and every single one of them had to be tested by sort.
Every one.
So the context of discretes?? and high volume??.
Been there, did it for a living.
jn
Ginetto61, I understand your frustration. If you really want to know about the Blowtorch, then reading the first 100 pages of Part 1 is best.
Now, this is an attempt for a hi tech, hi end forum, but it is diluted by people who don't believe that hi end is real, and that mid-fi is totally adequate, and people who just like to take a poke at me. This can lead to spirited discussion, but usually just dilution and confusion, obscuring anything that I might be able to offer that might improve someone's electronics.
Of course, at first, there was the challenge to get me to release the schematics and to help others to make their own Blowtorch. But now that is over, and we do share a few interesting ideas fairly often, but you have to be interested in a number of topics to make it a useful use of time to read.
Now, this is an attempt for a hi tech, hi end forum, but it is diluted by people who don't believe that hi end is real, and that mid-fi is totally adequate, and people who just like to take a poke at me. This can lead to spirited discussion, but usually just dilution and confusion, obscuring anything that I might be able to offer that might improve someone's electronics.
Of course, at first, there was the challenge to get me to release the schematics and to help others to make their own Blowtorch. But now that is over, and we do share a few interesting ideas fairly often, but you have to be interested in a number of topics to make it a useful use of time to read.
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You've clearly not read what I wrote or tried to explain.
Who said anything about not testing?
We were talking about wafer probe, and why process control (and by implication tight process limits) in very high volume were important. I do not recall saying anything about not testing devices - that's done 100 % after assembly. We spoke about binning. I've explained that the processes are so tightly controlled that the binning can be accurately projected from process data.
You've now introduced axial devices. Most discrete volumes today are in SMD.
11 million diodes a day is 3.5 billion a year. The industry ships a trillion devices a year currently with many suppliers now shipping tens of billions a year. These levels demand some pretty fundamental performance improvements over what the industry was doing 20 years ago.
You've adopted a position and seem hell bent on scoring points or whatever.
But, thankfully I can just dial out of this.
Who said anything about not testing?
We were talking about wafer probe, and why process control (and by implication tight process limits) in very high volume were important. I do not recall saying anything about not testing devices - that's done 100 % after assembly. We spoke about binning. I've explained that the processes are so tightly controlled that the binning can be accurately projected from process data.
You've now introduced axial devices. Most discrete volumes today are in SMD.
11 million diodes a day is 3.5 billion a year. The industry ships a trillion devices a year currently with many suppliers now shipping tens of billions a year. These levels demand some pretty fundamental performance improvements over what the industry was doing 20 years ago.
You've adopted a position and seem hell bent on scoring points or whatever.
But, thankfully I can just dial out of this.
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