I have a transport + separate non-os dac combo with I2S connection.
Now I am going to put the master clock in the dac unit and slave it in the transport. Masterclock is 16.934400 MHz and the bitclock required by the dac chip (TDA1541A) is 2.822400 MHz. So I need to divide masterclock by six. The 74LS92 can do the job but:
HOW MUCH JITTER DOES THE DIVIDER INTRODUCE?
Best regards.
Paul
Now I am going to put the master clock in the dac unit and slave it in the transport. Masterclock is 16.934400 MHz and the bitclock required by the dac chip (TDA1541A) is 2.822400 MHz. So I need to divide masterclock by six. The 74LS92 can do the job but:
HOW MUCH JITTER DOES THE DIVIDER INTRODUCE?
Best regards.
Paul
I was about to ask the same question as I have a similar configuration.
Probably some logic families are better than others, and I suppose a very clean power supply is mandatory. Hard to predict the jitter if you don't know the environment the chip will work in.
Right now I'm digging out the LC clock schematics. If I remember correctly, Lars used some logic chips, too, and he did jitter measurements.
Probably some logic families are better than others, and I suppose a very clean power supply is mandatory. Hard to predict the jitter if you don't know the environment the chip will work in.
Right now I'm digging out the LC clock schematics. If I remember correctly, Lars used some logic chips, too, and he did jitter measurements.
Lars used the following output buffers:
LClock1 / LClock2: 74AC02
LClock XO / LClock XO2: 74AHC1G04
LClock XO3: 74LVC1G02
Ask Jocko and Elso.
LClock1 / LClock2: 74AC02
LClock XO / LClock XO2: 74AHC1G04
LClock XO3: 74LVC1G02
Ask Jocko and Elso.
Sandor said:
Hi
The induced jitter depends on
- package size (inductance)
- logic family
- layout (external supply decoupling)
- supply noise (an inverter has only 6 dB PSRR)
- external circuitry like series resistors
Typically I'd suggest HC logic for the speed required, and use one package per divide step, preferably picogates. Ofcourse go for low noise, as with 1V/ns at the output you get 1 ps for each mV on te supply line......
NEVER use a string type divider like 393 here
You may consider reclocking the divided clock, just before it enters the 1541
Hope all helps
Hello Guys,
Guido, what would you suggest for 24Mhz (and beyond) division and buffering?
Do you have any data to show us?
Regards,
Mark Hathaway
Guido, what would you suggest for 24Mhz (and beyond) division and buffering?
Do you have any data to show us?
Regards,
Mark Hathaway
Mark Hathaway said:
Hi
You won't make it with HC so AC or ACT is the way to go. Go for SMD or single D flipflops like picogates
No data to share
cheers
dumb questions
Thank you all for replies.
Guido:
series resistors increase jitter?
How can I simply implement a divider-by-six ?
What is a string divider? 7492 belongs to this family?
Regards.
Paul
Thank you all for replies.
Guido:
series resistors increase jitter?
How can I simply implement a divider-by-six ?
What is a string divider? 7492 belongs to this family?
Regards.
Paul
Re: dumb questions
http://www.webmedia.pl/maciejza/zaplecze/img/schemat/teac_vrds_25x.gif
The section in the linked schematic consisting of U103A & B (74HC112) forms a divide-by-three circuit. Connect the output of this circuit i.e Q (pin 9) of U103B to the clock input of a D type flip, e.g. a 74HC74, with its /Q output connected to its D input and the Q output will be the clock input divided by 2 giving an overall divide-by ratio of 6. The are probably better ways to do it, you could decode the Q outputs of a '163 counter (note uneven M/S ratio)but this is as good a place as any to start.
Sandor said:
http://www.webmedia.pl/maciejza/zaplecze/img/schemat/teac_vrds_25x.gif
The section in the linked schematic consisting of U103A & B (74HC112) forms a divide-by-three circuit. Connect the output of this circuit i.e Q (pin 9) of U103B to the clock input of a D type flip, e.g. a 74HC74, with its /Q output connected to its D input and the Q output will be the clock input divided by 2 giving an overall divide-by ratio of 6. The are probably better ways to do it, you could decode the Q outputs of a '163 counter (note uneven M/S ratio)but this is as good a place as any to start.
Re: clock duty cycle
Hi
Most DACs convert on either positive or negative slope, so no importance
regards
Sandor said:
Hi
Most DACs convert on either positive or negative slope, so no importance
regards
Re: dumb questions
Hi
Series resistors reduce the RF content of the current so they can reduce the jitter. In turn, jitter can increase due to added thermal noise and or reduced slope (the receiving circuit then increases the jitter).
7492: May be OK, never tried one, otherwise use Google and Dflipflops
cheers
Sandor said:
Hi
Series resistors reduce the RF content of the current so they can reduce the jitter. In turn, jitter can increase due to added thermal noise and or reduced slope (the receiving circuit then increases the jitter).
7492: May be OK, never tried one, otherwise use Google and Dflipflops
cheers
74AC and ACT logic is very noisy and effectively obsolete these days. The transient current spikes as the outputs switch will not help to keep clean low-jitter outputs.
If you have to use a 5V Vdd rail then I suggest you look at 74VHC logic. This is the same speed as AC but is much quieter.
Even better would be to use the industry-standard 3.3V Vdd rail and use a modern logic family like 74LCX or 74LVC. (although this may not be possible if you are interfacing with old digital equipment that is using a 5V logic supply)
If you have to use a 5V Vdd rail then I suggest you look at 74VHC logic. This is the same speed as AC but is much quieter.
Even better would be to use the industry-standard 3.3V Vdd rail and use a modern logic family like 74LCX or 74LVC. (although this may not be possible if you are interfacing with old digital equipment that is using a 5V logic supply)
Re: Re: clock duty cycle
So you would regard L/R clock with a 9:1 M/S ratio as a good idea?
Guido Tent said:
So you would regard L/R clock with a 9:1 M/S ratio as a good idea?
Sandor said:
Your setup as I understand it, is a transport connected to a dac via I2S. You now wish to discard the BCLK connection that accompanies DATA and WDCLK and direct inject a new BCLK signal derived from a standalone clock. If this is what you plan to do be aware the three I2S signals function in sync with each other.
Re: Re: Re: clock duty cycle
Hi
No, but I wouldn't mind 40/60
Some oscillators have different jitter at positive or negative slope by the way.......(something you would NEVER reveal with a frequency domain analysis)
cheers
rfbrw said:
Hi
No, but I wouldn't mind 40/60
Some oscillators have different jitter at positive or negative slope by the way.......(something you would NEVER reveal with a frequency domain analysis)
cheers
Re: Re: Re: Re: clock duty cycle
I can think of at least one situation where the dac would not work correctly with that ratio.
Guido Tent said:
I can think of at least one situation where the dac would not work correctly with that ratio.
Re: Re: Re: Re: Re: clock duty cycle
Yes, It'll depend on the DAC.
My clocks are quite close to 50/50
regards
rfbrw said:
Yes, It'll depend on the DAC.
My clocks are quite close to 50/50
regards
Clock
Hi guys,
A resistor behaves like an inductor at HF (with some capacitance dominated by lead separation) so the HF currents are reduced.
The resistor may also develop a small voltage across itself which is then dependant on the quality of supply and output impedance of driving device. This can add noise to the input and make the jitter worse.
However the fundamental problem with adding a resistor is that it interacts with the inherent Cbe/Cgs of the input stages of subsequent devices. This causes an RC effect that is solely dependant on an extremely variable value of capacitance (of internal BJT/FET bases/gates).
Inserting a resistor isnt a problem as long as supplies are tidy, devices are adequately decoupled, and the value is kept no bigger than around 470R (I have used 100R with no worsening of jitter). However a trick those with a power electronics background (like myself) use frequently is to 'swamp' the Cbe/Cgs with a small external capacitor. This then fixes the RC constant to the values chosen (or near enough to dominate the base/gate capacitances).
One last thing that is an important consideration. Keep the trace lengths short. Inductance is not your friend in this case, as resonances my occur.
Also of note is that for most high speed stuff, your grounding of said signals will be more of an issue than jitter introduced by adding resistors/capacitors/dividers etc in the signal lines (assuming you have adequately decoupled the devices. Pay attention to return current paths, ac (dc) current will follow the path of least inductance (resistance). No cuts in ground plane over clock traces! Or you'll create loop antennae and radiate noise all over the place - and that will screw any potential jitter improvements up well and good!!!
Good luck
apollyon25
Hi guys,
A resistor behaves like an inductor at HF (with some capacitance dominated by lead separation) so the HF currents are reduced.
The resistor may also develop a small voltage across itself which is then dependant on the quality of supply and output impedance of driving device. This can add noise to the input and make the jitter worse.
However the fundamental problem with adding a resistor is that it interacts with the inherent Cbe/Cgs of the input stages of subsequent devices. This causes an RC effect that is solely dependant on an extremely variable value of capacitance (of internal BJT/FET bases/gates).
Inserting a resistor isnt a problem as long as supplies are tidy, devices are adequately decoupled, and the value is kept no bigger than around 470R (I have used 100R with no worsening of jitter). However a trick those with a power electronics background (like myself) use frequently is to 'swamp' the Cbe/Cgs with a small external capacitor. This then fixes the RC constant to the values chosen (or near enough to dominate the base/gate capacitances).
One last thing that is an important consideration. Keep the trace lengths short. Inductance is not your friend in this case, as resonances my occur.
Also of note is that for most high speed stuff, your grounding of said signals will be more of an issue than jitter introduced by adding resistors/capacitors/dividers etc in the signal lines (assuming you have adequately decoupled the devices. Pay attention to return current paths, ac (dc) current will follow the path of least inductance (resistance). No cuts in ground plane over clock traces! Or you'll create loop antennae and radiate noise all over the place - and that will screw any potential jitter improvements up well and good!!!
Good luck
apollyon25
470 ohms is a bit high............100 ohms is probably a decent upper limit. The idea is to slow down the spikes on the power and ground pins, without slowing it down to where the reduced slope enters in.
The less going on in the chip, the better. Picogates are your friends here................
Also explains why filter chips make rotten clock sources, and why designers who think that they are smarter than Guido's employer, use a 74HC04 for the clock.
Then proceed to muck it up anyway...........
Jocko
The less going on in the chip, the better. Picogates are your friends here................
Also explains why filter chips make rotten clock sources, and why designers who think that they are smarter than Guido's employer, use a 74HC04 for the clock.
Then proceed to muck it up anyway...........
Jocko
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