Hi,
I’m curious and would like to know (or measure) the impedance of a IXTP08N100D2 CCS (Depletion MOSFET) at various frequencies.
It’s not in the datasheet as far as I can see.
https://nl.mouser.com/datasheet/2/240/Littelfuse_Discrete_MOSFETs_N-Channel_Depletion_Mo-1856012.pdf
Regards, Gerrit
I’m curious and would like to know (or measure) the impedance of a IXTP08N100D2 CCS (Depletion MOSFET) at various frequencies.
It’s not in the datasheet as far as I can see.
https://nl.mouser.com/datasheet/2/240/Littelfuse_Discrete_MOSFETs_N-Channel_Depletion_Mo-1856012.pdf
Regards, Gerrit
datasheet
Fig 6.
Note that for 20kHz audio you are probably limited by Coss = 24pFd. And then by board cleanliness, humidity, etc etc.
The plots would be more useful with the test conditions given!
the "700V - 100V" label suggests a ramp was used; but the slope would have been helpful. Also, the assumed external gate resistance. Many constructors add oversized gate stoppers to Depletion-FET gates, which can degrade the HF performance of anode-load CCSs (Crss - Rg feedback). 100Ω is usually plenty for these FETs, even down to zero at low currents with carefully placed, short gate wiring.
Probably best to measure, using your design Vds and gate circuit.
the "700V - 100V" label suggests a ramp was used; but the slope would have been helpful. Also, the assumed external gate resistance. Many constructors add oversized gate stoppers to Depletion-FET gates, which can degrade the HF performance of anode-load CCSs (Crss - Rg feedback). 100Ω is usually plenty for these FETs, even down to zero at low currents with carefully placed, short gate wiring.
Probably best to measure, using your design Vds and gate circuit.
I don't see why. Or why resistors and capacitors useful in real circuits would be part of a device specification.700V - 100V" label suggests a ramp was used
But yes, I am inferring more than the sheet-writer intended. And we won't be building test-jigs but amplifiers. While I ssupect "it does not matter", I agree that measuring IS a good idea.
Could you look at figure 2 and the slope of the line near the operating point? For example, at a Vds of 50V and 0.4A (Vgs of -1V) the line is relatively flat, indicating high impedance. One could calculate the slope or the R. How would you measure it with varying frequency? I am really asking.
No capacitors, only the gate resistor. Maybe I am spoiled, but I am used to seeing Test Circuits for plots of dynamic parameters, on any data sheet, including FETs.. See for example ST's N-Channel 11NM80: See page 9 Test Circuits STW11NM80 .why resistors and capacitors useful in real circuits would be part of a device specification.
How would you measure it with varying frequency? I am really asking.
- set up the FET as CCS, with source resistor to suit the desired current;
- Use a (power) resistor in the drain to set a drain to source voltage that matches your application;
- Add a current sense resistor in the drain lead: 10Ω or whatever suits your scaling;
- Connected a battery-powered signal source. Neg supply to test rig neg. capacitor couple (and diode protect) signal output - to the sense resistor. Add a power follower if you want to drive larger signals.
- Apply a small signal from the signal source, measure voltage and current at the drain, use ohm's law, repeat for each frequency.
In cascode, end to end capacitance is significantly lower... 🙂 Mind yer gate stoppers.
Douglas
Douglas
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