Voltage clamp. I used a multiple-transistor version to clamp the voltage input to an ADC. The max-voltage wasn't a simple N*Vd situation.
In that application I wasn't too concerned about the clamp voltage variation over temperature. "N" wasn't particularly high. But I wanted it to REALLY clamp once it began to turn on, hence the multiple-transistor scheme.
One potentially significant drawback, at least for a simple 1-transistor multiplier, is that the temperature coefficient is multiplied too. In terms of being a problem it totally depends on what the application is. For setting bias current in a power amplifier: usually OK, since the multiplication factor is pretty-near the number of EF transistors you've got downstream from there. As a voltage reference: uh-uh, unless you need some PTAT action to compensate for some other circuit's tempco. Depending on what it needs to drive, a 2 or 3-transistor topology can get you a much lower tempco. But.....at that point, why bother unless you have other requirements that a voltage regulator chip can't provide?
In that application I wasn't too concerned about the clamp voltage variation over temperature. "N" wasn't particularly high. But I wanted it to REALLY clamp once it began to turn on, hence the multiple-transistor scheme.
One potentially significant drawback, at least for a simple 1-transistor multiplier, is that the temperature coefficient is multiplied too. In terms of being a problem it totally depends on what the application is. For setting bias current in a power amplifier: usually OK, since the multiplication factor is pretty-near the number of EF transistors you've got downstream from there. As a voltage reference: uh-uh, unless you need some PTAT action to compensate for some other circuit's tempco. Depending on what it needs to drive, a 2 or 3-transistor topology can get you a much lower tempco. But.....at that point, why bother unless you have other requirements that a voltage regulator chip can't provide?
If you change a simple Vbe multiplier just a little bit you can make something like this:
Now it is a synthetic inductor. And a fairly large one, at that. As shown this is not a practical application for oh so many reasons but that's an exercise left for the student to complete 🙂.
I once had the "fun" of finding a fault in a complex on-chip active filter that used gyrators. The whole thing was direct-coupled and had many feedback loops, so the circuit fault propagated in both directions. EVERY node in that sucker was screwed up. I finally resorted to using circuit simulation, deliberately creating a fault and then seeing if the behavior was similar to the real device. I jumped for joy when I nailed that one.
It turned out to be an open via located between two capacitors. The inter-layer dielectric was thicker there due to the way the ILD is deposited (it sort of "flows" into low spots), and the etch step used to create the vias wasn't quite long enough -- so it didn't make it all the way down to the bottom metal layer. Since it was a layout-dependent problem the failure signature was unique -- which did help a bit in terms of narrowing down the scope of the problem. Still, w/o simulation tools I was literally up the creek without a paddle.
Now it is a synthetic inductor. And a fairly large one, at that. As shown this is not a practical application for oh so many reasons but that's an exercise left for the student to complete 🙂.
I once had the "fun" of finding a fault in a complex on-chip active filter that used gyrators. The whole thing was direct-coupled and had many feedback loops, so the circuit fault propagated in both directions. EVERY node in that sucker was screwed up. I finally resorted to using circuit simulation, deliberately creating a fault and then seeing if the behavior was similar to the real device. I jumped for joy when I nailed that one.
It turned out to be an open via located between two capacitors. The inter-layer dielectric was thicker there due to the way the ILD is deposited (it sort of "flows" into low spots), and the etch step used to create the vias wasn't quite long enough -- so it didn't make it all the way down to the bottom metal layer. Since it was a layout-dependent problem the failure signature was unique -- which did help a bit in terms of narrowing down the scope of the problem. Still, w/o simulation tools I was literally up the creek without a paddle.
So this thing multiplies more then the Vbe, but also the thermal re and the tempco. Something to keep in mind.
Tuned around 120Hz implies a large inductor indeed! The trick is the inverting transistor: it inverts C1 too into that inductor. Nice application.
Great story, impressive finding. Cheerio!
You're right:
The derivative of Ic = Is * { ( e^(q*Vbe/k*T)-1} to the temperature T yields into ς (sigma = d(Ic)/d(T))= qVbe/kT^2 * Ic
In other words, the T appears squared in the denominator making it very sensitive to thermal variance.
And also true, it depends on the application - have that Vbe multiplier stuck on the heat sink for proper thermal feedback!
It relieves the general/overall feedback from it, and leaving that mechanism to control the desired amplification, distortion suppression and dc stability (three tasks already...).
Yes. The variation over temperature sorts itself out because the output transistors have the same temperature dependency. Roughly. Isat is going to be different because it is proportional to the junction area. The impact will be the same as found (and employed) in current mirrors since it isn't inside the exponential term. Isat DOES have its own temperature dependency but fortunately its equation doesn't include a Vbe term. The bandgap voltage, yes.