Hello all,
I've been working on a design for a Class D Amp using the IRS2092 to drive a 1Ohm Subwoofer load. I was hoping I could get some feedback on it from some people that know more than me, as this is my first design. Thanks a ton to Eva, Mag, and all the others that I've benefited from while reading through these forums.
Currently I'm laying out the PCB. Wish PADS had an auto-place for some of the small resistors
More information on the project can be found here: http://beaversource.oregonstate.edu/projects/44x200914/wiki
The goal is to eventually get this amp above 500W.
Thanks!
Brent Scrivner
I've been working on a design for a Class D Amp using the IRS2092 to drive a 1Ohm Subwoofer load. I was hoping I could get some feedback on it from some people that know more than me, as this is my first design. Thanks a ton to Eva, Mag, and all the others that I've benefited from while reading through these forums.
Currently I'm laying out the PCB. Wish PADS had an auto-place for some of the small resistors
More information on the project can be found here: http://beaversource.oregonstate.edu/projects/44x200914/wiki
The goal is to eventually get this amp above 500W.
Thanks!
Brent Scrivner
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Thanks for the optimism. I just ordered the pcb about 15 hours ago. Good catch on the 47R, made me check my parts list. I actually ordered a 4r7, that was just a typo.
I'm not looking forward to testing the protections. Thinking of putting the protection signal connecting diode on headers for easy removal
I'm not looking forward to testing the protections. Thinking of putting the protection signal connecting diode on headers for easy removal
Hmm. Don't know enough about this to tell if that is going to be a show stopper. How badly do traces that long affect the output. If I dropped the carrier frequency down lower could that help mitigate that problem?
Why you guys never CARE TO READ application notes related with that driver chip and a basic understanding of RF and switching electronics is must prior to any adventure of this much calibre.
The forum is FILLED with numerous examples, seems you havent done your homework.
I have read all of the related application notes. Care to make any suggestions for improvements? I do not have a fundamental understanding of RF and switching electronics as they are not currently in my major. I will be studying those in years to come.
Minimise gate/source trace length
Minimise the switching node area between mosfets also
and a solid grounplane is a must
besides this there are many key factors which fall under basic switching electronics fundamentals. I am surprised how you took class-d as your project without knowing these.
Give the guy a break; the world with not implode in on itself if his project fails.
If you think he doesn't deserve your input, then don't give any input.
Ok lets waste money
Thanks for the feedback. It's brutal, but I knew it was coming
One problem I was having with the layout of the FETs was since I was using single TO-220 heatsinks I valued not overlapping the footprints of those. If I had access to a solid custom drilled heatsink I probably could have done a lot better. Was there a way I missed that I could move the FETs closer together without screwing up the cooling?Workhorse said:Minimise the switching node area between mosfets also
Is trying to do this on a 2-layer board pointless? I've heard "use a 4 layer board" before but that wasn't an option. Or, did I just lay it out that poorly and could have gotten away with 2 layers but didn't.Workhorse said:and a solid grounplane is a must
I'm ambitious? This subject really interests me, and I figured I'd go for it. Go big or go home, right? Unfortunately, I've been studying computer networks and IC design, not power electronics, so I've missed a lot of the RF subject matter.Workhorse said:I am surprised how you took class-d as your project without knowing these.
Thanks for the feedback. It's brutal, but I knew it was coming
One problem I was having with the layout of the FETs was since I was using single TO-220 heatsinks I valued not overlapping the footprints of those. If I had access to a solid custom drilled heatsink I probably could have done a lot better. Was there a way I missed that I could move the FETs closer together without screwing up the cooling?
Is trying to do this on a 2-layer board pointless? I've heard "use a 4 layer board" before but that wasn't an option. Or, did I just lay it out that poorly and could have gotten away with 2 layers but didn't.
I'm ambitious? This subject really interests me, and I figured I'd go for it. Go big or go home, right? Unfortunately, I've been studying computer networks and IC design, not power electronics, so I've missed a lot of the RF subject matter.
At least read IR app notes on class-d amps on www.irf.com under audio section, you will learn a great deal as a beginner.
I have read those, and specifically in AN-1135 a star ground is recommended instead of a ground plane. Most reference designs I've seen though use a ground plane.
I guess a couple revisions I would make now are make the bottom middle plane at -B and the top at +B instead of both at the same reference and break up the ground plane a bit around the input circuitry.
Not sure how I could move the FETs in and shorten the gate traces without finding a better heatsink solution. Getting the FETs in D-FET packaging would've allowed me to shorten the traces to within an inch but I don't have any sinks for those. That was my logic at least, not trying to defend it.
I guess a couple revisions I would make now are make the bottom middle plane at -B and the top at +B instead of both at the same reference and break up the ground plane a bit around the input circuitry.
Not sure how I could move the FETs in and shorten the gate traces without finding a better heatsink solution. Getting the FETs in D-FET packaging would've allowed me to shorten the traces to within an inch but I don't have any sinks for those. That was my logic at least, not trying to defend it.
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