Good day,
I built a class D amp everything is working but when I test the gate driver (IR2110) and MOSFETs (15V), the driver no longer outputs any signals and it decreases the VCC voltage (12V) to 4.9V. I have dead-time so I don’t know what is causing this.
Switching frequency: 30 kHz
Ir2110 output peak to peak is 20v and not 12v.
I built a class D amp everything is working but when I test the gate driver (IR2110) and MOSFETs (15V), the driver no longer outputs any signals and it decreases the VCC voltage (12V) to 4.9V. I have dead-time so I don’t know what is causing this.
Switching frequency: 30 kHz
Ir2110 output peak to peak is 20v and not 12v.
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Sorry, for not included more information. The schematic can be seen in the pdf. I change the dead-time to the one in the second page. I added the deadtime after the LM311n comparator. I need to design a H bridge hence the reason for the deadtime. I have a common ground in the circuit, this ground the low side MOSFETs and the scopes at one point in the circuit. This voltage drop I'm experiencing means the driver is damaged or the driver's undervolatge lockout activated. When the 12 volt supply is not connected, the PSu reads 12 but when connected decreases to 4.9v.
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Right now you only have one half of the H bridge running? Must be shoot-through.
Can you do a floating measurement of the upper gate-source voltage waveform?
Have you tried a 1N4148 across each output gate resistor (with the anode to the gate)?
Some dead time in hardware is always best.
Can you do a floating measurement of the upper gate-source voltage waveform?
Have you tried a 1N4148 across each output gate resistor (with the anode to the gate)?
Some dead time in hardware is always best.
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I can do a floating measurement gate-source voltage waveform, if you simply explain how to perform the test.
Shoot-through? But I have dead-time and the inputs waves are inverse and doe snot start the same time, it is quite noticeable.
I tried the HIp4081A first but never got it to work. I don't want to blow more drivers to I'm trying to find an answer for the 12V voltage drop.
Shoot-through? But I have dead-time and the inputs waves are inverse and doe snot start the same time, it is quite noticeable.
I tried the HIp4081A first but never got it to work. I don't want to blow more drivers to I'm trying to find an answer for the 12V voltage drop.
Compare the upper and lower gate-source waveforms directly on the scope,
aligning them so the zero voltage levels coincide, and be sure they do not overlap enough
to cause shoot through. Without a negative turn-off voltage, this becomes more critical.
Where is the current limit set on the power supply, try increasing it a little.
Try the 1N4148 diodes, they ensure a fast turn-off.
aligning them so the zero voltage levels coincide, and be sure they do not overlap enough
to cause shoot through. Without a negative turn-off voltage, this becomes more critical.
Where is the current limit set on the power supply, try increasing it a little.
Try the 1N4148 diodes, they ensure a fast turn-off.
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Install the two 1N4148 diodes next, like this:
http://4.bp.blogspot.com/-GZBCM0xlSbk/UPvnSo5w4rI/AAAAAAAAAZo/YUTt0KpFnPA/s1600/IR2110+block.png
Does the 2110's Vdd (usually pin 9) drop, too (when the Vcc drops to 4.9V)? What does it measure then?
What family are the logic gates (Schmitt triggers and inverters) you showed in your deadtime thumbnail? If they're slow (compared to MOSFETS running at 30kHz), the extra full-gate delay may be causing unexpected trouble. They need to use the same supply voltage as the 2110's Vdd, pin 9.
The 1N4148's across the 10R gate drive resistors as shown by rayma is probably a more reliable and direct deadtime solution than the RC/Schmitt trigger delays -- especially since a Gate-stopper resistor is needed anyway.
Cheers
What family are the logic gates (Schmitt triggers and inverters) you showed in your deadtime thumbnail? If they're slow (compared to MOSFETS running at 30kHz), the extra full-gate delay may be causing unexpected trouble. They need to use the same supply voltage as the 2110's Vdd, pin 9.
The 1N4148's across the 10R gate drive resistors as shown by rayma is probably a more reliable and direct deadtime solution than the RC/Schmitt trigger delays -- especially since a Gate-stopper resistor is needed anyway.
Cheers
If you're already running Vdd at 5V, I'd change to 74HC14's or similar -- but it really HAS to be a Schmitt trigger. That delay technique is clever and handy, but yields inconsistent delays. Also, the positive-going threshold is different than the negative-going threshold, which complicates design. Still worse, 4000-series parts are dreadfully slow on 5 Volts. If you want to continue testing before fitting an HC Schmitt trigger, just bump your Vdd up to the 12V Vcc or even 15V. The 4069 will then provide adequate (for testing) speed.
I can't guarantee it or present the math, but I've sure seen it a lot in commercial designs, both H-bridge and half-bridge. The latter have very much the same issue with deadtime.
I think there's something else loading your Vcc ..
Regards
I can't guarantee it or present the math, but I've sure seen it a lot in commercial designs, both H-bridge and half-bridge. The latter have very much the same issue with deadtime.
I think there's something else loading your Vcc ..
Regards
Sorry I'm just getting to your full schematic from post #3 ..
The 4070 XOR is better than a 4069 could do -- that way there isn't an extra gate delay in just one path. Still probably oughta run it on more than 5V.
I hope the actual delay is implemented more like the thumbnail schematic, and not like the full schematic. In the latter, C5 and C6 won't affect the delay until RP1 and RP2 are so low that the driving gate is excessively loaded, which will add more jitter and unpredictability to the timing. And the delay will be similar for both edges (except for differences due to threshold asymmetry).
C8 and C11, at 22 uF, may be too big, and an electrolytic is unwise. Bigger isn't always better. It only needs to have enough capacitance to provide the current to overcome the Gate capacitance, one cycle at a time. The high-frequency performance is the most important attribute; next is probably stability over temperature. There are some good app notes on this -- probably from TI -- sorry I don't have the link for you.
R1 is superfluous. If you like it for good reason, put a matching one on the other line.
Now for the real problem: The full schematic shows no ground connection for the IR2110's at all!
Both COM and Vss must have a firm ground. That alone could explain the symptoms you described.
Best Luck
The 4070 XOR is better than a 4069 could do -- that way there isn't an extra gate delay in just one path. Still probably oughta run it on more than 5V.
I hope the actual delay is implemented more like the thumbnail schematic, and not like the full schematic. In the latter, C5 and C6 won't affect the delay until RP1 and RP2 are so low that the driving gate is excessively loaded, which will add more jitter and unpredictability to the timing. And the delay will be similar for both edges (except for differences due to threshold asymmetry).
C8 and C11, at 22 uF, may be too big, and an electrolytic is unwise. Bigger isn't always better. It only needs to have enough capacitance to provide the current to overcome the Gate capacitance, one cycle at a time. The high-frequency performance is the most important attribute; next is probably stability over temperature. There are some good app notes on this -- probably from TI -- sorry I don't have the link for you.
R1 is superfluous. If you like it for good reason, put a matching one on the other line.
Now for the real problem: The full schematic shows no ground connection for the IR2110's at all!
Both COM and Vss must have a firm ground. That alone could explain the symptoms you described.Best Luck
it was ground when testing, I just quickly drew up that schematic.
What bootstrap capacitor do you recommend for 30 kHz.
When I tried the Xor gate circuit with the ir2110, it resulting in a lot of overshooting in the outputs and also between the MOSFETs. That was the reason for the change of dead-time circuits.
I'm gonna have to hunt down that App Note; 30 kHz is lower than usual.
I didn't mean to recommend the XOR circuit as is. Just observing that it can provide approximately matching delays when one channel becomes two -- one Inverting, one Not Inverting. Not sure what you mean by 'overshooting in the outputs', but within one family -- 4000-series, 74HC, etc -- the wave shape coming out of the single-edge-delay circuit *should* be the same. The capacitor-in-series/trimpot-to-ground won't do what you need. The approach shown in the original thumbnail, signal passing through paralleled diode/trimpot then to small capacitor with its other leg grounded, WILL.
Why the choice of rather low 30 kHz? Is this to drive a sub channel, perhaps? It'll make the output filter quite a bit more expensive - and bulky.
edit: The UF4007 is unsuitable for this delay circuit. Score a couple 1N4148's or something else in the 50 - 100V PIV / 25 - 100 mA range -- much lower capacitance and storage time.
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Exactly what do you mean "test the gate driver"? Sounds like it is going into latch-up (very bad). If so, a stronger supply will just do more damage. This usually happens when you connect a transient that exceeds the supply rail to any pin.
BTW, a xx4007 is not fast enough for audio, much less PWM. It will not turn off before it needs to come on again.
BTW, a xx4007 is not fast enough for audio, much less PWM. It will not turn off before it needs to come on again.
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