Hi
I am currently building the input stage for a Class-D sigma-delta modulator amp in an FPGA (If this rings a bell, I am Gretzteam's partner in this crazy adventure!). Anyways, the CS8414 Digital Audio Receiver from Cirrus Logic seems seems like a logical 😉 choice. I have read a lot on the AES-S/PDIF protocol and decide it would be wiser to use this chip instead of implementing it on the FPGA. Anyone has experience with that chip?
From what I have seen in the datasheet(http://www.cirrus.com/en/pubs/proDatasheet/8413-4.pdf), I should select Mode 0, which outputs the clocks (FSYNC and SCK) and 16 bit interleaved left-right audio data. Is this right? I also plan on hardwiring the SEL pin to ground to get the error and frequency reporting option (although I do not plan to really use it as our input will only be from a cd player).
I want the simplest implementation possible. In other words: Should I (Can I?) leave the User Bit pin and all Channel Status pins (Output, block start, channel select) floating and not bother with them. I know about the SCMS stuff but do I need to deal with it?
Once done, I need a serial to parrallel converter (FPGA implemented) From what I see, there is no start/stop bit. Is FSYNC good enough to guide me through left/right channel switching. What about reseting? How long (clock cycles) should I reset the chip on a power-up?
Any ideas and/or comments would be greatly appreciated!
Thanks
SpeedWheel
I am currently building the input stage for a Class-D sigma-delta modulator amp in an FPGA (If this rings a bell, I am Gretzteam's partner in this crazy adventure!). Anyways, the CS8414 Digital Audio Receiver from Cirrus Logic seems seems like a logical 😉 choice. I have read a lot on the AES-S/PDIF protocol and decide it would be wiser to use this chip instead of implementing it on the FPGA. Anyone has experience with that chip?
From what I have seen in the datasheet(http://www.cirrus.com/en/pubs/proDatasheet/8413-4.pdf), I should select Mode 0, which outputs the clocks (FSYNC and SCK) and 16 bit interleaved left-right audio data. Is this right? I also plan on hardwiring the SEL pin to ground to get the error and frequency reporting option (although I do not plan to really use it as our input will only be from a cd player).
I want the simplest implementation possible. In other words: Should I (Can I?) leave the User Bit pin and all Channel Status pins (Output, block start, channel select) floating and not bother with them. I know about the SCMS stuff but do I need to deal with it?
Once done, I need a serial to parrallel converter (FPGA implemented) From what I see, there is no start/stop bit. Is FSYNC good enough to guide me through left/right channel switching. What about reseting? How long (clock cycles) should I reset the chip on a power-up?
Any ideas and/or comments would be greatly appreciated!
Thanks
SpeedWheel
DIR1701 and DIR1703 would also be good choices. They have less jitter than Crystal's recievers. If you want compatibility with 192 kHz sampling rate you should use CS8416.
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