Hi, in the diagram a part of amplifier below you can see circuit current source arrangement that is used for an input stage and the VAS as same use 2 diodes .
My question is : Why they not connect from B on T3 with T4 to reduce using separate R1, R2 , 2 diodes.
My question is : Why they not connect from B on T3 with T4 to reduce using separate R1, R2 , 2 diodes.
Probably to prevent an undesired stable bias point/circuit latch-up.
Suppose the circuit is driven into clipping to the negative rail. T4 then goes into saturation and will draw much more base current than normal, in the worst case almost all of its emitter current could flow through the base. This could pull down the base voltage, and with common diodes, that would reduce the current through T3. If the current through T3 is reduced so much that T5 cannot turn on anymore, the circuit will latch up in this state, that is, stay there indefinitely.
Suppose the circuit is driven into clipping to the negative rail. T4 then goes into saturation and will draw much more base current than normal, in the worst case almost all of its emitter current could flow through the base. This could pull down the base voltage, and with common diodes, that would reduce the current through T3. If the current through T3 is reduced so much that T5 cannot turn on anymore, the circuit will latch up in this state, that is, stay there indefinitely.
The negative railm CCS voltage diodes are fed from the positive rail through R2, this has no i,nfluence on the differential CCS
reference wich is fed separtaely with R1.
The two diodes in the VAS input act along with its emitter resistance as a current limiter, that s the reason why they are implemented.
The current through T1 cant exceed 2mA or so, so there would be up to 4.4V at the VAS input and about 3.7V on its emitter resistance of 90R, wich would result in a 40mA peak current when clipping and assuming that the output stage will drain this current.
The two diodes limit the base voltage at 1.3V, wich will limit the emitter voltage to 0.65V across the resistance, hence limiting the VAS peak current to 7mA, in principle the VAS current limitation should slightly exceed the negative rail CCS current capability, for this reason the VAS emitter resistance should be a little lower than the CCS emitter resistance.
reference wich is fed separtaely with R1.
The two diodes in the VAS input act along with its emitter resistance as a current limiter, that s the reason why they are implemented.
The current through T1 cant exceed 2mA or so, so there would be up to 4.4V at the VAS input and about 3.7V on its emitter resistance of 90R, wich would result in a 40mA peak current when clipping and assuming that the output stage will drain this current.
The two diodes limit the base voltage at 1.3V, wich will limit the emitter voltage to 0.65V across the resistance, hence limiting the VAS peak current to 7mA, in principle the VAS current limitation should slightly exceed the negative rail CCS current capability, for this reason the VAS emitter resistance should be a little lower than the CCS emitter resistance.
Thank for answer .
but I mean base voltage at T3 & T4 is same around 1,3V . that can connect base T3 with T4 and remove 1 line (R and 2 diodes).
becasue i saw it in other amplifier ( Nmos200)
but I mean base voltage at T3 & T4 is same around 1,3V . that can connect base T3 with T4 and remove 1 line (R and 2 diodes).
becasue i saw it in other amplifier ( Nmos200)
In this latter case what MarcelvdG talked about fully apply, since there s no separation between the two CCSs references
the transistor on the right, T7, wich load a VAS, can drain the whole reference voltage cureant and render the input differential
non functional, in such occurence the amp output can stick to one voltage rail as long as the VAS is kept switched off.
the transistor on the right, T7, wich load a VAS, can drain the whole reference voltage cureant and render the input differential
non functional, in such occurence the amp output can stick to one voltage rail as long as the VAS is kept switched off.
Does the other amplifier happen to have a current mirror on top of its input differential pair? If so, it probably remains functional with a much reduced current through T4.
Yes , it have . even without current mirror you still get CCS input by 2 diodes fix 1,3V at B on T3 ( with R 300ohm) and CCS on VAS by T4.
yes , did you mean when at negative T4 at saturation the voltage at base can drop make reduce voltage to T3 ?
My very first bipolar chip design (a bio-impedance processor) did bias up by spice in a non desired state. so I forced spice to bias up as intended. It turned out exactly what Marceld described, and could latchup once the custom (test)-chip was built. I always believe spice dc-op solutions ever since.
Even if SPICE ends up in the desired bias point without help, you may still have a problem. When the circuit has several bias points, a circuit simulator more or less randomly converges to one of them and doesn't warn you about the existence of the others. It also doesn't care whether the bias point it finds is stable or metastable.
A Mexican chap called Arturo Sarmiento-Reyes worked on an algorithm to find all of a circuit's bias points in the early 1990's. It got him a PhD, but I'm not aware of any commercial software including his algorithm.
At work, I usually simulate start up and recovery from positive and negative clipping and hope for the best. Large-signal instabilities are also usually found that way.
A Mexican chap called Arturo Sarmiento-Reyes worked on an algorithm to find all of a circuit's bias points in the early 1990's. It got him a PhD, but I'm not aware of any commercial software including his algorithm.
At work, I usually simulate start up and recovery from positive and negative clipping and hope for the best. Large-signal instabilities are also usually found that way.
If the ~diode current is greater than the VAS current, then the entire VAS emitter current can come from the base without losing the diode voltage, but this is wasteful. Some amps put a series resistor in the VAS CCS base to limit the base current to less than the reference current and may include a Baker clamp. Extending the base resistor to a divider allows the LPT to operate before and after the VAS CCS to reduce turn-on/off thumps, ie the LTP maintains ~zero VDC output through VAS power-up/down, the LPT never loses control of the VAS.
True, but even with CMOS, there are still plenty ways to cause undesired stable bias points or large-signal oscillations.
Apparently I have been lucky eversince. My largest design was an electronic pricetag CMOS analog optical receive chain at 1.245Mhz. They sold 200M chips of it. Forgot to ask a percentage...
Typical example: CMOS fully differential amplifier with a common-mode loop that is designed such that a current source runs out of voltage headroom when the common-mode voltage is way off, as a result of which the common-mode loop then doesn't work. Add a transistor to detect this state and pull the amplifier out of it, and find that the loop dynamics are so different from normal operation that it oscillates and keeps oscillating when this transistor turns on.
Seem to solve the problem just connect ~ 1K (a series resistance) to B at T4 before connect to B on T3.