Improvement in VAS

[Bigun]

Interesting. I am intrigued by Q3 collector connected to R7.
Can you tell more about the performances of the circuit ?

R7 is part of the TPC. It isn't strictly needed for Q3 except it offers some token current limiting - traditionally the EF buffered VAS arrangement leads to fried parts under extreme conditions. There are some subtleties here, the collector doesn't simply present it's parasitics to the compensation network, there is a signal at the collector of Q3.

The circuit simulates well and sounds very good indeed. I haven't spent a lot of effort exploring the limitations or quirks of the circuit but I found this arrangement to perform the best out of the related topologies I explored in Spice. The inspiration came from the SKA GB150for the bootstrapping the collector load of the input device - I looked at this option as far back as my TGM4 design. And I looked at this TPC arrangement a couple of years ago at least and it's on a thread around here somewhere.

 

[jcx]

missed my post? - if you want current limit add a separate collector R - its not like they cost anything, a small C too for AC gnding

but you really aren't "bootstrapping" the input Q collector to the right V to improve anything - why involve any of its nonlinear Zcb or deliberately add Early modulation of its hfe, hoe is also uncertain and nonlinear so I don't see a good reason to put it into the TPC node - the Cce is nonlinear with
V too

can you demonstrate improved performance of your connection over the "conventional" EF buffer enhanced VAS?

 

[Bigun]

missed my post? - if you want current limit add a separate collector R - its not like they cost anything, a small C too for AC gnding

but you really aren't "bootstrapping" the input Q collector to the right V to improve anything - why involve any of its nonlinear Zcb or deliberately add Early modulation of its hfe, hoe is also uncertain and nonlinear so I don't see a good reason to put it into the TPC node - the Cce is nonlinear with
V too

can you demonstrate improved performance of your connection over the "conventional" EF buffer enhanced VAS?

I once made a suggestion in one of the DX destroyer threads how to limit the collector current of a EF buffer - tie it to the output instead of to ground. I never tried it, but it works in simulations.

The bootstrapping bit is easy to see in Spice where you can measure currents more easily than in practice - the current variations through Q1 are smaller.

I can't demonstrate any improved performance of my connection

 

[jcx]

a way to test in spice is to replace various stages with ideal controlled sources - I think you will most often find that "perfect" VAS Spice dependent source model with the same gm, input Z doesn't really make an audio frequency difference in most amp circuits - output stage nonlinearities, output stage nonlinear load on the VAS dominate most amps

the increased gain of the Beta enhanced circuit can help - changes both Zin and gm of the stage

after that Cascoding the VAS output can help if the output stage is sufficiently buffered so that its nonlinear load on the VAS isn't dominating - but you have to get that right 1st

 

[panson_hk]

Example in attachments.

Thanks for your file. Did you simulate for component mismatch scenario? The result may closer to real world performance. Correct?

 

[nigelwright7557]

I have found using a single transistor creates more than enough gain.
In fact I was having to use a CB capacitor to slow it down !
Seems pointless adding lots of gain if due to oscillation you have to slug it with a capacitor.
What can happen is the output overshoots due to too much gain.
This because the feedback loop has a time constant.
This causes over shoot on the outputs.

 

[jcx]

there are fetishists who don't like seeing highly linear, few % tolerance, sized to the circuit functional demand compensation C on their schematic - preferring to rely on improperly sized Q too large parasitic Ccb which is noninear with Vcb

but I'm not sure what they have to contribute to a "Improvement in VAS" thread


I don't agree with every detail of Doug Self's Audio Power Amplifier Design Handbook - but it is good baseline to start profitable discussion from - he does show the advantages of various VAS enhancements - with real circuit performance plots

even the few lines, plots in http://www.douglas-self.com/ampins/dipa/dipa.htm could help the level of discussion

 

[John_wr]

I want to say that so many of these advanced VAS circuits are actually overkill for good audio performance in the real world. Most of the distortion comes from the output stage, and D.Self acknowledges this in his book there is no reason for anything really esoteric here. Miller capacitance linearity (aka Hawkesford's transistor slope distortion) can be measureable in ideal conditions. In my view all that is really needed its lots of open loop gain and single pole frequency compensation. D.Self advocates the addition of a buffer transistor, but it can still be engineered to have the desired effect whether the buffer is placed inside the VAS local feedback loop or even after the VAS output.

 

[BV]

Thanks for your file. Did you simulate for component mismatch scenario? The result may closer to real world performance. Correct?

For optimal results it is always needed to set close to optimal operating points. Real results are about 2-3 times worse, depends on transistors used and mainly on PCB topology. For minimal distortions PCB become very important circuit "component".

 

[BV]

Most of the distortion comes from the output stage, and D.Self acknowledges this in his book there is no reason for anything really esoteric here.

Reality is that in majority of "real" amplifiers most of all kinds of distortion results from poor engineering and circuit design..Also relative very simple classB EF output topology can reach distortion about 0,001-0,002% at 20kHz, from 1mW Pout to full Pout..

 

[John_wr]

Reality is that in majority of "real" amplifiers most of all kinds of distortion results from poor engineering and circuit design..Also relative very simple classB EF output topology can reach distortion about 0,001-0,002% at 20kHz, from 1mW Pout to full Pout..

I just wonder if you are agreeing with me that VAS design is adequate, or are you still looking for further reduction in distortion?

 

[BV]

VAS design is adequate, if VAS (and input) distortion (and mains artifacts , from poor PSRR and bad wiring..) is not a big (dominating) part of resulting distortion of whole amplifier. I should to write that
"Reality is that in majority of "real" amplifiers most of all kinds of distortion results from poor engineering and circuit design in stages before output stage."
But we can say the less, the better..

 

[Bigun]

Dr. Self looks at each stage of the amplifier and explains it very well, he shows clearly that you can reduce the distortion of each stage so much that the output is the only worry left to deal with (Class AB). On this basis, a single VAS devices is fine. But he does point out that in his opinion, the best way to deal with distortion from a Class AB output stage is lots of negative feedback. Hence, it's not just the linearity of the VAS I look at because I believe that it's desirable to have a high OLG from the front-end of the amplifier, with minimal phase issues - i.e. stable. You can choose to use this OLG to linearize the front-end and run the back end open loop, or you can choose to use this OLG to linearize the whole amplifier - all depending on your goals. I wanted to linearize the whole amplifier, hence the 3-transistor front-end design I used in TGM8. And TGM7 follows a similar philosophy. I do use some nested feedback in TGM8 (a recommendation from Hugh Dean) but both TGM7 and TGM8 are high-feedback designs and the sound of them has persuaded me that high-feedback is not a dirty word 😀 But it starts with a front-end capable of clean high OLG.