Hello.
Trying to make a simple 8-bit R2R DAC for fun.
R2R works, but it converts a parallel byte to analog, right?
How do I convert an I2S stream into parallel? I suppose I should use shift registers or something, but i don' t know exactly what to do.
Trying to make a simple 8-bit R2R DAC for fun.
R2R works, but it converts a parallel byte to analog, right?
How do I convert an I2S stream into parallel? I suppose I should use shift registers or something, but i don' t know exactly what to do.
Use something like a 74HC595. Clock data into the i/p shift reg with bit clock then use word clock to transfer the data to the o/p latches.
input and output.
Specifically with a serial->parallel shift register chain (like the '595) you'd put BCLK into its clock, DATA into its serial input, and using LRCLK as
the latch signal. Add an inverter to LRCLK to get the other channel into another shift register chain. As always careful scrutiny of the datasheet is needed to check that this will do the right thing (maybe some clocks need to be inverted? ie. check whether rising or falling edges are needed in each case.
Specifically with a serial->parallel shift register chain (like the '595) you'd put BCLK into its clock, DATA into its serial input, and using LRCLK as
the latch signal. Add an inverter to LRCLK to get the other channel into another shift register chain. As always careful scrutiny of the datasheet is needed to check that this will do the right thing (maybe some clocks need to be inverted? ie. check whether rising or falling edges are needed in each case.
Your DAC design needs to process a 2's complement bipolar data input format. In addition, I2S streams are 64-bit frames, each comprised of two 32-bit half-frames (one half frame per stereo channel). Each 32-bit half frame's serial audio sample data arrives MSB first, and is at least 16-bits per sample, so you'll need to account for that in the serial conversion to an 8-bit parallel input.
Of course the delay in that inverter will be detrimental, you'll need to delay the other signals to compensate as having skew in the MSB is the worst place to have it. Might want a DQ latch after the inverter stage to remove skew?