Hi,
In one of the other posts, i announced i was working on splitting
the I2S signal for two DAC's. One for left channel and one for rightchannel. I am going to use this for a 2 times TDA1514 non-os
DAC, but it should work for other DACs aswell. Please no discussion here on DAC's, but only on the splitting of I2S.
I have a testcircuit working and made a small site for it.
Have a look: http://www.home.zonnet.nl/baltusg/I2S.html
The circuit contains a GAL, but without some 'features' it should be possible to use standard logic. It can 'split' the incoming I2S into two new I2S signals. One has two times left channel samples and the other right channel. So i now have a TDA1541 for left channel and one for the right channel. The outputs of one DAC can then be joined together.
One of the features is to invert one of the samples in the outgoing I2S, creating differential output at the DAC.
This inverting does not take the LSB in account, so it is one LSB off. But i think i can reprogram the GAL to fix that without much hassle. Will be in v2 soon...
Greetings,
Guido
In one of the other posts, i announced i was working on splitting
the I2S signal for two DAC's. One for left channel and one for rightchannel. I am going to use this for a 2 times TDA1514 non-os
DAC, but it should work for other DACs aswell. Please no discussion here on DAC's, but only on the splitting of I2S.
I have a testcircuit working and made a small site for it.
Have a look: http://www.home.zonnet.nl/baltusg/I2S.html
The circuit contains a GAL, but without some 'features' it should be possible to use standard logic. It can 'split' the incoming I2S into two new I2S signals. One has two times left channel samples and the other right channel. So i now have a TDA1541 for left channel and one for the right channel. The outputs of one DAC can then be joined together.
One of the features is to invert one of the samples in the outgoing I2S, creating differential output at the DAC.
This inverting does not take the LSB in account, so it is one LSB off. But i think i can reprogram the GAL to fix that without much hassle. Will be in v2 soon...
Greetings,
Guido
hi,
Had another look at differential mode. The dataline is inverted when wordselect AND the delayed wordselect are low. This means the ('left' frame is inverted, except the LSB.
Just like it should be when two's complement is to be inverted !!
BUT, my SAA7210 has a 32 bit frame, so not the LSB is 'not inverted', but the last 'dummy' bit. So i am one LSB off after all.
If i want to fix this, i would need to make something with a counter (counting to 16).
Too much hassle for now, everybody just inverts the whole dataline anyway. The DAC accuracy might be even les than 1 LSB...
But if your I2S signal does not have the 'fillers', it should be the exact inverse of a two's complement, going into the 'left' channel of both DAC's.
Greetings,
Guido
Had another look at differential mode. The dataline is inverted when wordselect AND the delayed wordselect are low. This means the ('left' frame is inverted, except the LSB.
Just like it should be when two's complement is to be inverted !!
BUT, my SAA7210 has a 32 bit frame, so not the LSB is 'not inverted', but the last 'dummy' bit. So i am one LSB off after all.
If i want to fix this, i would need to make something with a counter (counting to 16).
Too much hassle for now, everybody just inverts the whole dataline anyway. The DAC accuracy might be even les than 1 LSB...
But if your I2S signal does not have the 'fillers', it should be the exact inverse of a two's complement, going into the 'left' channel of both DAC's.
Greetings,
Guido
guido,
I don't know if it is of use to you but John westlake did something like that in the cambridge cd6. Though he used tda1305 dacs. These where used in a differential mode as well by feeding the left channel the inverted signal i think. I don't know how it works but i might have the schematic somwhere even though it will take me some time to find it (just moved). If you're interested let me know.
greetings Joris
I don't know if it is of use to you but John westlake did something like that in the cambridge cd6. Though he used tda1305 dacs. These where used in a differential mode as well by feeding the left channel the inverted signal i think. I don't know how it works but i might have the schematic somwhere even though it will take me some time to find it (just moved). If you're interested let me know.
greetings Joris
Hi,
Eric, what are you looking for, designs with TDA1541 or designs in general with a dac in differential mode?
As for the last category, you can get a dac with differential out (most modern dacs i think) or take two mono DACs per channel and use some logic to invert the datasignal towards one DAC. The Pass D1 uses fore times PCM63 in this way.
As for the other replies. I am shure i did not invent the wheel and that there are other designs doing more or less the same. I just thought it would be an improvement to DACs with two times TDA1541.
But it could be usefull for others too.
Greetings,
Guido
Eric, what are you looking for, designs with TDA1541 or designs in general with a dac in differential mode?
As for the last category, you can get a dac with differential out (most modern dacs i think) or take two mono DACs per channel and use some logic to invert the datasignal towards one DAC. The Pass D1 uses fore times PCM63 in this way.
As for the other replies. I am shure i did not invent the wheel and that there are other designs doing more or less the same. I just thought it would be an improvement to DACs with two times TDA1541.
But it could be usefull for others too.
Greetings,
Guido
Guido,
I am trying to do something similar to you, i.e. split up an I2S or right justified (I don't care) signal into L/-L and R/-R to feed into two AD1853s. AD suggests this can be done but fails to provide a schematic.
For the Pass D1, it was easier because the signal was inverted after the digital filter.
Eric
I am trying to do something similar to you, i.e. split up an I2S or right justified (I don't care) signal into L/-L and R/-R to feed into two AD1853s. AD suggests this can be done but fails to provide a schematic.
For the Pass D1, it was easier because the signal was inverted after the digital filter.
Eric
Eric,
The pass uses a NPC digital filter (U5) which has separate data output for left and right. The left output is then fed to one DAC, the inverse of left to number two and the same for right channel.
So if you don't want to use such a dig filter, you need something like my circuit to split the I2S. Had a look at the CS8414. It also has 32 bit per frame. Seems to be standard.
Guess my circuit is ok to use, if we can find some bigger shift registers (hopefully 32 bit). One other possiblity is to put all of the logic into one big modern chip. I used the GAL because i had a programmer and some chips lying around. And it is easier for prototyping, modern stuff seems to be 84 pin SMD minimal..
And yes, the principal stays the same..
I am still looking into getting the inverse completely right, but it probably means more logic.
Greetings,
The pass uses a NPC digital filter (U5) which has separate data output for left and right. The left output is then fed to one DAC, the inverse of left to number two and the same for right channel.
So if you don't want to use such a dig filter, you need something like my circuit to split the I2S. Had a look at the CS8414. It also has 32 bit per frame. Seems to be standard.
Guess my circuit is ok to use, if we can find some bigger shift registers (hopefully 32 bit). One other possiblity is to put all of the logic into one big modern chip. I used the GAL because i had a programmer and some chips lying around. And it is easier for prototyping, modern stuff seems to be 84 pin SMD minimal..
And yes, the principal stays the same..
I am still looking into getting the inverse completely right, but it probably means more logic.
Greetings,
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