Hi all...
I just want to make sure i get this correct before i go making up PCBs.
The SPDIF Recv (DIR1703) has the I2S lines labled as:
LRCLK - Left/Right clock
BCK - Bit clock
SCKI - System clock
DATA - Data
The TAS3001 is labled as:
LRCLK - Left/Right clock
DATA - Data in
MCLK - Master clock
SCLK - Shift clock (bit clock)
Am i correct in thinking that:
DIR1703 -> TAS3001
BCLK -> SCLK
SCKI -> MCLK
?
Thanks.
I just want to make sure i get this correct before i go making up PCBs.
The SPDIF Recv (DIR1703) has the I2S lines labled as:
LRCLK - Left/Right clock
BCK - Bit clock
SCKI - System clock
DATA - Data
The TAS3001 is labled as:
LRCLK - Left/Right clock
DATA - Data in
MCLK - Master clock
SCLK - Shift clock (bit clock)
Am i correct in thinking that:
DIR1703 -> TAS3001
BCLK -> SCLK
SCKI -> MCLK
?
Thanks.
Hi MWP
I believe you're right.
If you look at table 5 on page 9 (DIR1703 datasheet) you can see that SCKO, BCKO and LRCKO are 256(128, 384, 512)x fS, 64 x fS and 1 x fS respectively. This means that SCKO must be the "master clock" (it has the highest integer multiple of fS. If fS=44,1kHz, then 256 x fS is 11,2896MHz). BCKO will be 11,2896/4=2,8224MHz, which is right when the format dictates 64 bit frames (32bit per channel - max. 24 bit audio wordlength!).
If you look page 2-1 in the section "Audio data formats" (TAS3001 datasheet) you'll see in line 5: "If the
256 × fs MCLK is selected, CLKSEL is tied low and an MCLK of 256 times the sampling frequency must be supplied.
In both cases, an LRCLK of 64 × SCLK must be supplied." Now we are confused!! A LRCLK of 64 x SCLK (which is 64 x fS) will be 4096 x fS, huh... I don't think so.
The datasheet states some lines below that MCLK=256 x fS (ussually), SCLK=64 x fS and LRCLK is the same as fS. Stick with that.
If you calculate these frequencies, as above, with 44,1kHz you'll see the light.
That leads us what you´ve stated:
SCKO - MCLK
BCKO - SCLK
LRCKO - LRCLK
Another thing, be sure to check the polarities of the signals. You could end up having switched L to R and R to L, but more importantly you can lose you MSB!!!!
Regards,
Kasper
I believe you're right.
If you look at table 5 on page 9 (DIR1703 datasheet) you can see that SCKO, BCKO and LRCKO are 256(128, 384, 512)x fS, 64 x fS and 1 x fS respectively. This means that SCKO must be the "master clock" (it has the highest integer multiple of fS. If fS=44,1kHz, then 256 x fS is 11,2896MHz). BCKO will be 11,2896/4=2,8224MHz, which is right when the format dictates 64 bit frames (32bit per channel - max. 24 bit audio wordlength!).
If you look page 2-1 in the section "Audio data formats" (TAS3001 datasheet) you'll see in line 5: "If the
256 × fs MCLK is selected, CLKSEL is tied low and an MCLK of 256 times the sampling frequency must be supplied.
In both cases, an LRCLK of 64 × SCLK must be supplied." Now we are confused!! A LRCLK of 64 x SCLK (which is 64 x fS) will be 4096 x fS, huh... I don't think so.
The datasheet states some lines below that MCLK=256 x fS (ussually), SCLK=64 x fS and LRCLK is the same as fS. Stick with that.
If you calculate these frequencies, as above, with 44,1kHz you'll see the light.
That leads us what you´ve stated:
SCKO - MCLK
BCKO - SCLK
LRCKO - LRCLK
Another thing, be sure to check the polarities of the signals. You could end up having switched L to R and R to L, but more importantly you can lose you MSB!!!!
Regards,
Kasper
- Status
- Not open for further replies.