Just ask AI to do it. A nice hallucination would feel better (but may not work). What is the part number of the probe? Is it set up for a 1 meg or a 50 Ohm input? Some of the aftermarket probes really do not perform as advertised.
Regarding fast risetimes, I agree it can cause problems without much if any benefit. Maybe risetime matters for the one clock signal the dac chip used for final conversion, but most of the other signals can be beneficially slowed down. It is not too uncommon to see people using 100R series damping resistors instead of the usual 33R or so.
A lot about how to get a dac sounding good is suggested in my clock thread and in Cestrian's clock and reclocking board thread. Everyone who has tried it so far has been impressed with the sound over what they were able to do before. Cleaner, more realistic sound. Also, soundstage tightens up in precision, and deepens as well.
The thing to remember is that dacs and dac clocking it not exactly the same as high-speed digital. Rather with dac clocking its more like low noise analog RF with square-ish signals.
https://www.diyaudio.com/community/threads/general-purpose-dac-clock-board.413001/
https://www.diyaudio.com/community/...r-jlsounds-i2soverusb-pcm2dsd-rtz-dac.423401/
A lot about how to get a dac sounding good is suggested in my clock thread and in Cestrian's clock and reclocking board thread. Everyone who has tried it so far has been impressed with the sound over what they were able to do before. Cleaner, more realistic sound. Also, soundstage tightens up in precision, and deepens as well.
The thing to remember is that dacs and dac clocking it not exactly the same as high-speed digital. Rather with dac clocking its more like low noise analog RF with square-ish signals.
https://www.diyaudio.com/community/threads/general-purpose-dac-clock-board.413001/
https://www.diyaudio.com/community/...r-jlsounds-i2soverusb-pcm2dsd-rtz-dac.423401/
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Indeed, this is probably a lost cause. But for different reasons. You don't need to see "clean edges" to know your timing jitter. That's because this is digital signaling. Your endpoint doesn't care. The DAC is not going to have problems with jitter until the entire edge's slope is shifting back and forth, at which point even a 50 MHz BWL scope can see it.
Try using just one probe. That'll quadruple your bandwidth or total storage duration limit.
My suggestion? Reduce your digital signal's drive current unless you need it that high. That'll reduce your ringing and jitter, and make for a very consistent slope. More current is not more betterererer here. (edit: seems like I forgot to scroll to the second page. Others have suggested this as well!)
I would have to strongly disagree. Clock jitter in DACs, ADCs, ASRCs, and DDSs, is a more complex subject than most seem to be aware of. Its just as important as Vref amplitude noise. An error in time, or more correctly a correlated series of small errors in time (phase noise) can fold down into the audio band and cause noise to intermodulate with the dac's audio signal, just the same as with Vref (amplitude noise). The effects can be seen in spectral line noise skirts. Sometimes they even use the noise skirt view at ASR as a more sensitive measure of jitter than J-test can provide.
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Hi Mark,
There are limits where jitter doesn't matter if it is less than that. That is simply a fact of life. Humans simply are not sensitive phase discriminators and there is no reference clock in a human to sense it an any way. Period.
Hi APEXHiFi,
Controlled slew rate and reduced ringing is probably what your goal should be. Digital signals have pretty good noise immunity which is why analogue computers are not the dominant technology. Mind you, PAM 8 encoding is diving back into the analogue world with both feet. You won't see PAM 6 or PAM 8 any time soon, that's between chips and in data centers coming out. We are currently at PAM 4. PAM 4 is way beyond what you are doing.
You would need extreme ringing to cause data errors. Besides, connecting anything in the way of a probe to that path will probably introduce more reactive elements and cause ringing that wouldn't normally be there. It depends on the frequencies you're dealing with, which you still haven't mentioned. There is no way to gauge the degree of potential problems without knowing that. But how the edge looks, as others have mentioned, isn't that important. After the edges, that is important.
There are limits where jitter doesn't matter if it is less than that. That is simply a fact of life. Humans simply are not sensitive phase discriminators and there is no reference clock in a human to sense it an any way. Period.
Hi APEXHiFi,
Controlled slew rate and reduced ringing is probably what your goal should be. Digital signals have pretty good noise immunity which is why analogue computers are not the dominant technology. Mind you, PAM 8 encoding is diving back into the analogue world with both feet. You won't see PAM 6 or PAM 8 any time soon, that's between chips and in data centers coming out. We are currently at PAM 4. PAM 4 is way beyond what you are doing.
You would need extreme ringing to cause data errors. Besides, connecting anything in the way of a probe to that path will probably introduce more reactive elements and cause ringing that wouldn't normally be there. It depends on the frequencies you're dealing with, which you still haven't mentioned. There is no way to gauge the degree of potential problems without knowing that. But how the edge looks, as others have mentioned, isn't that important. After the edges, that is important.
Hi Chris,
I get the message I am not supposed to argue with you even if you are dead wrong. I'm out.
Best,
Mark
I get the message I am not supposed to argue with you even if you are dead wrong. I'm out.
Best,
Mark
Yup!
Isolate the probe capacitance from the circuit. We often use a 100R resistor in series with a 10:1 probe for this.
Again, no idea about the frequencies involved, or rise time.
Isolate the probe capacitance from the circuit. We often use a 100R resistor in series with a 10:1 probe for this.
Again, no idea about the frequencies involved, or rise time.
Why isn't the same problem with video signals? Why doesn't anyone there, absolutely no DIY-er, discuss jitter reduction? Why can everything be done there with "classic" circuits, so to speak, without audiophile nonsense.
And yet there we are really talking about many GIGAhertz bandwidth, not just a few tens of KILOhertz.
Simple: because the jitter problem is not actually a real problem if well-designed circuits are used, the jitter problem is a fake problem to extort money from snobby audiophiles.
@APEXHiFi
To see signals with a 500+Mhz band cleanly without setup ringing you have to use active differential probes of at least 2.5Ghz and an oscilloscope of at least 2.5-5Ghz, and something like that is extremely expensive for an amateur, maybe only if you sell a kidney. Anyway, I don't think you are using a correct measurement setup for this frequency range and, moreover, it is a false problem.
And by the way, measure the DACs you make with universal spectrum analyzers with a minimum bandwidth of 3.5Ghz (10hz-3.5Ghz) not with audio spectrum analyzers. You will be amazed how much high frequency garbage reaches their output and then ends up in the amplifiers where it creates other problems, unknown to most. And that's how you start to hear cables.
Regarding jitter, you really need to make a distinction between the jitter that corresponds to close-in phase noise and the jitter that corresponds to the phase noise floor, and between many-bit DACs and DACs involving some sort of sigma-delta modulation.
Regarding the original subject, I think I would use a makeshift voltage divider consisting of two physically small resistors, and a thin semirigid coaxial cable, all to be soldered to the board closely to the point under test. The first resistor reduces the load on the driving circuit, the second matches the impedance to the characteristic impedance of the cable to the oscilloscope. The semirigid cable's shield can be soldered straight to a PCB ground plane after scratching off some solder mask.
Regarding the original subject, I think I would use a makeshift voltage divider consisting of two physically small resistors, and a thin semirigid coaxial cable, all to be soldered to the board closely to the point under test. The first resistor reduces the load on the driving circuit, the second matches the impedance to the characteristic impedance of the cable to the oscilloscope. The semirigid cable's shield can be soldered straight to a PCB ground plane after scratching off some solder mask.
I wonder... are you using the wrong type of device for measuring what happen to be square wave logic signals?
At work we use logic analyzers, not "signal scopes". We routinely get clear, sharp pictures of GHz clock signals.... I guess I've never thought about it, but yeah the physics of it indicate very high bandwidths.
Naturally, you (nor I) can afford those logic analyzers. But.... just a heads up...
Here is some info on the scope TDS754 and upgrading it to 1 GHz: https://www.eevblog.com/forum/testgear/conversion-of-500mhz-tds744a-to-1ghz-tds784a/ There are some risetime pictures that suggest the scope is pretty clean. And other useful bits on checking and calibrating it.
I'm using slower rise times in a lot of the circuitry, but for the final PDM stage of my DAC just before the analogue filter where timing jitter and signal levels are critical, I was aiming for as close to true square as possible. I intend to experiment to see whether fast is good here or whether using slower but extremely consistent does the same job.
N.B. with a Pulse Density Modulation "single bit" DAC design like this, the signal timing is an inherent part of the analogue output, so phase jitter on the clock in this final stage has a pretty profound impact on sound quality. It's very measurable as output distortion even with a cheap FFT-based spectrum analyser so I'm aiming for as good as I can get timing-wise.
Changing crystals from cheap ones to oscillators with 1ps phase jitter made a very noticeable difference and I'm working at present with a manufacturer who can get me crystals made with 50fs phase jitter. Of course consistency in the width and shape of the pulses is the problem, not timing accuracy per-se, so square edges may be better, or may be worse. They are, however, less likely to introduce phase jitter in the final drive stage which is why I'm experimenting.
Changing crystals from cheap ones to oscillators with 1ps phase jitter made a very noticeable difference and I'm working at present with a manufacturer who can get me crystals made with 50fs phase jitter. Of course consistency in the width and shape of the pulses is the problem, not timing accuracy per-se, so square edges may be better, or may be worse. They are, however, less likely to introduce phase jitter in the final drive stage which is why I'm experimenting.
It isn't the clock edge you need to worry about. The following circuits have already triggered and will completely ignore pulse shape after that unless you fall below the other threshold. The converse is true if you work with the falling edge. Noise on the slopes near the switching point will cause jitter for sure as that translates into a timing error. But the actual pulse edges are basically invisible, rounded or ringing slightly will not show up anywhere.
Yes, age old problem with "single bit" technology. Multibit and single bit each have their possible issues.
Yes, age old problem with "single bit" technology. Multibit and single bit each have their possible issues.
That's not actually the case here. There are no following digital circuits. The sharp edges are the last bit of digital circuitry. It goes straight into a low pass analogue filter from there.
Okay, but in that case you are worried more about "energy under the curve". The edges represent an area that will be filtered out.
True if they are totally consistently shaped and perfectly timed. Which is far from guaranteed. That's exactly what I'm experimenting with in this design. Do I get better performance with very sharp edges, along with all of the resonances and other nasties, or do I get better performance with slower edges and the potential problems that asymmetrical rise and fall times give which will result in nonlinearities in the final output.