How to design a discrete opamp with Rail to Rail output?

Use two common-emitter or common-source stages, one NPN or NMOS and one PNP or PMOS. If it needs to work in class AB, you can add a class-AB control loop or make a Monticelli output stage, https://patents.google.com/patent/US4570128A/en The latter have been used all over the place since the National Semiconductor patent expired.

It may be a good idea to apply local feedback around the output stage at high frequencies, for example by Miller compensation, to make the overall loop gain less dependent on the load impedance and to make it vary less with signal. Mind the right-half-plane zero.
 
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By the way, an ordinary Sziklai pair/CFP type of output stage with a gain greater than 1 might also do the trick.

Unless it needs to keep working rail-to-rail for very low frequencies, you could even use a bootstrapped emitter follower on one side of a rail-to-rail output stage.
 
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