That statement is out of place. I AM running this amp. While choosing my compensation of 47pF, I ran a simulation for 39p and 47p ... neither oscillated but 39 showed damped ringing. On the real amp 39p produced a much warmer zoble /output stage and a "tinny" sound. The scope showed this as well (ringing). At the 47pF compensation all was good.
My conclusion is that if the simulator can can predict a 8pF difference in miller compensation correctly, then it can surely predict an 80 phase margin/3mhz unity gain change that I know would oscillate like hell.
I know by comparing simulations to real amps that all operating points can be predicted within millivolts (mV) and microamps (uA). You can also predict the gain and rolloffs (input filter/zoble - bandwidth) within a decible.Some models like the old mje340/350- 2n5550 - Bcxxx will simulate where as the real circuit will smoke. Those "silly" free simulators (LT) are way more accurate than multisim or other "bloatware" and dead even with Microcap (I have/stole that, too).. the corporate device model is what determines accuracy.
I DO concede that the sim can not predict layout parasitics or the final sound of the project. I do have a 20mhZ dual trace CRT , 2 DMM's ( I have an industrial electronics surplus shop down the road .. oak ridge , 3 universities)
... so for BJT's , I can see what's happening. I now have 3 amps at home and 8 at the local clubs , ALL work and work hard , so I guess I have also built something. I sometimes will push to the "edge" of compensation (no stupid 100pF millers) and luckily only fried a couple tweeters and a Zoble cap.
BTW , thank you for the tip on how to quickly make a oscillator out of a high loop gain audio amp.
I would prefer to use more elegant ways to reduce THD. (TMC)OS
Avoiding ground loops
Hi, Nico Ras, thanks for your comments.
Are you saying the 0V sides of r1/c2/c3/r4/r10/r5/r6/c8,9,12,13 (ie all parts in the input and driver stages) should be tied together and then go to 0V via a 10R?
Hi, Nico Ras, thanks for your comments.
Are you saying the 0V sides of r1/c2/c3/r4/r10/r5/r6/c8,9,12,13 (ie all parts in the input and driver stages) should be tied together and then go to 0V via a 10R?
bypass cap considerations...
Without values, what I'm saying here should be called typically reasonable generalizations, but your mileage may vary.
C5 has two classes of effects:
1. small signal phase margin
2. large signal simultaneous conduction of output transistors
Phase Margin stuff:
You say that C17 is a no-load. I'll assume that the amp is stable. That means that the dominant pole that's keeping it like that is the capacitive loading of the output fets Cgs and Cgd on the output of the Vas. I'll make some assumptions about values...R12 and R13 are 100 Ohms (?), as they're just "stopper" resistors on the gates. C6, without knowing its value, could be there for enhancing stabiity. (a lot of what I'm saying is guesses without seeing values).
Anyway...thing about the forward gain, starting from the base of Q9, with C5=0. Q11's capacitance puts a pole at the collector of Q9. If V2, a variable resistor, is un bypassed, then there's a second, separate pole, given very roughly by the value of V2 and the input capacitance of the N-channel fet and C6. That increases the phase lag in the forward path, giving less phase margin when the loop is closed.
Now, as you make C5>0, the two separate poles merge into 1 pole at a lower frequency than the two separate poles. Doing this gives a little more phase earlier, but less phase at higher frequencies, since there's now only one pole. C5 just has to be large enough to keep the phase margin happy for positive voltages on the load, when the top FET is on. The worst case will be when the output voltage is high enough to saturate the top FET, as the Cgd grows greatly, and non-linearly.
The other thing that C5 does, is it similarly improves the phase lag situation for the R15-C4 connection. That bit of feedback helps to keep the amp stable, since its some faster feedback that doesn't include the output stage. However, if C5 is zero, there will be more lag in the fast feedback, and it may not have the desired effect of adding stability.
Large Signal Simultaneous Conduction:
Assume that C5=0, and we're outputting a large positive voltage and current. Now the input calls for us to output a large negative voltage and current. Q9's collector swings low quickly, since it can develop a large voltage across the unbypassed V2 resistor. Now Q10 and Q11 are both on, since all the capacitance of Q10 tends to keep it turned on. So the second criterion to C5, is make it large enough to avoid simultaneous conduction on a quick switch from the top to bottom transistor.
Typically, all the phase margin and simultaneous conduction effects can be avoided with C5 in the region from about 0.1 uF to 0.01 uF.
Hope this helps...but if I can clarify things a bit more, please post...
Without values, what I'm saying here should be called typically reasonable generalizations, but your mileage may vary.
C5 has two classes of effects:
1. small signal phase margin
2. large signal simultaneous conduction of output transistors
Phase Margin stuff:
You say that C17 is a no-load. I'll assume that the amp is stable. That means that the dominant pole that's keeping it like that is the capacitive loading of the output fets Cgs and Cgd on the output of the Vas. I'll make some assumptions about values...R12 and R13 are 100 Ohms (?), as they're just "stopper" resistors on the gates. C6, without knowing its value, could be there for enhancing stabiity. (a lot of what I'm saying is guesses without seeing values).
Anyway...thing about the forward gain, starting from the base of Q9, with C5=0. Q11's capacitance puts a pole at the collector of Q9. If V2, a variable resistor, is un bypassed, then there's a second, separate pole, given very roughly by the value of V2 and the input capacitance of the N-channel fet and C6. That increases the phase lag in the forward path, giving less phase margin when the loop is closed.
Now, as you make C5>0, the two separate poles merge into 1 pole at a lower frequency than the two separate poles. Doing this gives a little more phase earlier, but less phase at higher frequencies, since there's now only one pole. C5 just has to be large enough to keep the phase margin happy for positive voltages on the load, when the top FET is on. The worst case will be when the output voltage is high enough to saturate the top FET, as the Cgd grows greatly, and non-linearly.
The other thing that C5 does, is it similarly improves the phase lag situation for the R15-C4 connection. That bit of feedback helps to keep the amp stable, since its some faster feedback that doesn't include the output stage. However, if C5 is zero, there will be more lag in the fast feedback, and it may not have the desired effect of adding stability.
Large Signal Simultaneous Conduction:
Assume that C5=0, and we're outputting a large positive voltage and current. Now the input calls for us to output a large negative voltage and current. Q9's collector swings low quickly, since it can develop a large voltage across the unbypassed V2 resistor. Now Q10 and Q11 are both on, since all the capacitance of Q10 tends to keep it turned on. So the second criterion to C5, is make it large enough to avoid simultaneous conduction on a quick switch from the top to bottom transistor.
Typically, all the phase margin and simultaneous conduction effects can be avoided with C5 in the region from about 0.1 uF to 0.01 uF.
Hope this helps...but if I can clarify things a bit more, please post...
Interesting topic and good explantation - this I miss in all me known books about amplifier. If you put in a serial resistor (e. g. 1 milli-ohms) by simulation, it is possible to perform an investigation about the current through this bypass capacitor. If I have time, I will do this. BTW - at topologies with BjT VBE multiplier this bypass capacitor is also to find (parallel to the C-E line).
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