i have been working on this project for a few days now and i managed to get to this, but there are a few things wrong with it.
im thinking about adding another gain stage and improving the constant current sink.
im thinking about adding another gain stage and improving the constant current sink.
Q2 will go up in smoke if you build it like this with discrete transistors. Q5 and Q2 need emitter resistors for thermal stability.
Does V2 have a -12 V DC value that isn't shown on the schematic? If not, the gate of J1 will be biased at 0 V (despite R11; there is no AC coupling, so R11 does nothing but load V2). J1 will then have an excessive gate current.
It's unclear to me what is meant to do what and how everything is biased. Could you plot a DC operating point and explain what the intention is?
Does V2 have a -12 V DC value that isn't shown on the schematic? If not, the gate of J1 will be biased at 0 V (despite R11; there is no AC coupling, so R11 does nothing but load V2). J1 will then have an excessive gate current.
It's unclear to me what is meant to do what and how everything is biased. Could you plot a DC operating point and explain what the intention is?
i definitly think i should use an op amp for the current sink (at least for now) also im to dumb to know what dc operating point is i used an emitter resistor once but i then realised i lack one in my part arsenal
.. or connect R11 and J1 source to ground, but a source resistor is required
which should be adjusted to suit your intended drain current.
This circuit has no regular feedback, so you can go around with a scope probe.
I suspect this is a simulator exercise only ?
How do you control output offset - via Q3 ?
Output stage bias current is set to 800 mA - a lot.
which should be adjusted to suit your intended drain current.
This circuit has no regular feedback, so you can go around with a scope probe.
I suspect this is a simulator exercise only ?
How do you control output offset - via Q3 ?
Output stage bias current is set to 800 mA - a lot.
A DC operating point is the same as a DC bias point, that is, just the combination of DC voltages and currents that you have when there is no signal. Simulators usually have a knob somewhere that makes them annotate the DC operating point on the schematic.
@as_audio Maybe you use a different definition of 'bias point' than what I'm used to, as I have no idea what you mean by post #9, but I would like to know the DC node voltages and branch currents with 0 signal. With that information, at least we won't have to reverse engineer which transistors are in saturation and which not.
This is essentially a voltage follower. Q4 is in deep saturation, so the signal goes via its base-collector diode, which shifts up the DC level by about 0.7 V. Emitter follower Q2 shifts it back. All in all, you get a voltage gain close to +1.
You could change Q4 into a PNP emitter follower to make the load on the signal source smaller: connect the base of Q2 to the emitter rather than the collector of Q4, replace R3 with a short circuit and increase R4 to 100 ohm or so.
More generally, I think it would be more useful for you to read a couple of books about analogue circuit design, rather than to keep simulating random permutations of transistors and resistors.
You could change Q4 into a PNP emitter follower to make the load on the signal source smaller: connect the base of Q2 to the emitter rather than the collector of Q4, replace R3 with a short circuit and increase R4 to 100 ohm or so.
More generally, I think it would be more useful for you to read a couple of books about analogue circuit design, rather than to keep simulating random permutations of transistors and resistors.
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