From https://neurochrome.com/pages/output-power#parallelBridgeBoth:
"Do note that when connecting two LM3886es in parallel, ballast resistors must be used to ensure that the two LM3886es share the load current evenly. Also note that the input voltage offset difference between the two LM3886es causes a standing current to flow through the ballast resistors. This standing current must be minimized to avoid excessive THD even at moderate output power levels. To accomplish this, the input offset of each LM3886 must be minimized, preferably using a DC servo thereby increasing the complexity of the circuit considerably."
I therefore wonder how bad will the standing current will be in the below schematics? Is servo absolutely necessary or I can do without?
Help much appreciated!
"Do note that when connecting two LM3886es in parallel, ballast resistors must be used to ensure that the two LM3886es share the load current evenly. Also note that the input voltage offset difference between the two LM3886es causes a standing current to flow through the ballast resistors. This standing current must be minimized to avoid excessive THD even at moderate output power levels. To accomplish this, the input offset of each LM3886 must be minimized, preferably using a DC servo thereby increasing the complexity of the circuit considerably."
I therefore wonder how bad will the standing current will be in the below schematics? Is servo absolutely necessary or I can do without?
Help much appreciated!
I looked it up for you in the data sheet ;-)
It is specified at 1mV typical, 10mV max.
The DC gain around the chip is 1, so worst case there would be 20mV difference between the two outputs, assuming max values and opposite polarity.
With 0.2R total ballast, that would, worst case, give I = V/R = 2*10^-2 / 2*10^-1 = 10^-1A = 100mA if I did my sums correctly.
That's a lot. But if you assume typical values that drops to 10mA.
There's also the input offset current, worst case 0.2uA, which would cause an offset voltage across the 10k feedback resistors of another (2*10^-7) * (10^4) = 2*10^-3 = 2mV. Typical value would be 1/20 of that.
I don't know if that would add or subtract, depends on polarity. Worst case it would add of course.
It would be very rare for two chips both being worst case offsets and opposite polarity, so I would go with typical values but do a health check after the build.
Maybe Tomchr has some info on the typical values he sees in his builds.
Jan
It is specified at 1mV typical, 10mV max.
The DC gain around the chip is 1, so worst case there would be 20mV difference between the two outputs, assuming max values and opposite polarity.
With 0.2R total ballast, that would, worst case, give I = V/R = 2*10^-2 / 2*10^-1 = 10^-1A = 100mA if I did my sums correctly.
That's a lot. But if you assume typical values that drops to 10mA.
There's also the input offset current, worst case 0.2uA, which would cause an offset voltage across the 10k feedback resistors of another (2*10^-7) * (10^4) = 2*10^-3 = 2mV. Typical value would be 1/20 of that.
I don't know if that would add or subtract, depends on polarity. Worst case it would add of course.
It would be very rare for two chips both being worst case offsets and opposite polarity, so I would go with typical values but do a health check after the build.
Maybe Tomchr has some info on the typical values he sees in his builds.
Jan
High output standing current is not necessary a bad thing. This current will keep the output stage in class A witch is required by some audiophile peoples.
Paralleling voltage sources usually have those kind of problems. From two batteries, two transformers, two amplifiers... Also usually it is done in order to get more power. But given you have all the circuit balanced to ground, keep it balance up to the output and bridge them in place of parallel them.
At DC, the like branches of the subtractor circuits are connected together, not to (AC-) GND as it were the case for AC. That might change the differential DC gain for DC offset, ideally you just insert a 10mV DC source at one single OpAmp input pin in the sim and check the outputs (I haven't checked).
Normally, we want to have each section use their own coupling caps so that there is no coupling at DC between sections. A servo (one per section) might be a better solution as the capacitors are smaller and can be precision type and tolerance, which avoids fighting conditions at near DC frequencies where cap tolerances will cause different output voltages leading to cross currents.
That said, I've paralled outputs of LM4780 duals with 0.1R in a composite and ran some 20 amplifier modules at 10x down to DC with no DC cross current issues, always less than 100mA. Not a guaranteed spec but with a bit of care I think you can eliminate all DC capacitors and run the circuit DC-coupled, placing an input DC cap at the input of the preceeding buffer.
OT but wanted to point out the input bias network formed by R3, R4 and R5.
I've advocated for this approach for a long time.
It has a high Zcm (and modest Zdiff) without using bootstrapping.
I've advocated for this approach for a long time.
It has a high Zcm (and modest Zdiff) without using bootstrapping.
Yes and much less than 1W, 0.5W or 0.25W or how much it will be.
Your point?
100mA or even more is often found in class AB amps.
Never in class A amps (except possible in headphone amps of course, there it can support class A).
Jan
Your point?
100mA or even more is often found in class AB amps.
Never in class A amps (except possible in headphone amps of course, there it can support class A).
Jan
Thanks everyone for replies!
So is it possible to match two LM3886 chips by offset voltage value? Will that be a good idea practically speaking?
So is it possible to match two LM3886 chips by offset voltage value? Will that be a good idea practically speaking?
In principle yes, but in practice you will have to build them, including soldering, mounting, smearing with grease, the works.
FWIW in my book paralleling voltage sources is bad engineering so I avoid it like the plague.
This silly idea became popular because chipamp sellers get to sell twice as many (or 4 times as much) and beginners find them simple and cool.
FWIW in my book paralleling voltage sources is bad engineering so I avoid it like the plague.
This silly idea became popular because chipamp sellers get to sell twice as many (or 4 times as much) and beginners find them simple and cool.
For a proper paralleling a kind of current share mechanics must be done. Ussualy there is an outer voltage loop controlling the gain and distortion but the is one or more internal current loop that tryes to distribute currents in all power devices more or less equaly. Unfortunately, the inner current loop must be done whit a BW somewhat more limited than the voltage loop in order to avoid oscillations.
As I said, use with care and always check independent offsets first before fitting the current sharing resistors.
There's plenty of instrumentation field amplifiers that use simple load sharing between a bunch of similar closed loop output stages, so I wouldn't say this is bad engineering per se.
On that end, one could even count paralleled output transistors or MOSFETs as paralleling voltage sources if one would go pedantic ;-)
In this case you are paralleling resistances, not voltage sources. This 8s why you use ballast resostors in emmiters. FET don't need the because of positive tempco.
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This is incorrect. It's about differences in gain and output voltages, not drift (which is about bias conditions running away with temperature).
Jan
You can split a supply like this, but you need to use a divider across the two rails for the positive inputs instead of a single resistor to the (floating) ground. Or you can add a ground ~regulator that soaks up any bias current that might pull ground towards one of the rails.
Not AT ALL, absolutely different case.
:
When paralleling power amplifiers, which is the case here, each one has its own "brain" (differential stage, main gain stage, most important: its own NFB net), hell bent on setting a definite output voltage.
Having 2 (or more) "brains" will result on them fighting each other to death to impose its own "solution"
I stand by my idea that paralleling voltage is a bad idea, bad Engineering, and recognize that in some limited cases it can be done, sort of, only becuse they deviate from being a perfect voltage source.
So they are not such any more, and hardly a rebuttal to my concept.
The clumsy cludgy way to (sort of) "solve" that very real problem, self created I might add, is to:
1) make those "fighting brains" think alike .... which is not easy:
a) use exact same type and model chipamps
b) use high precision (0.1%) resistors in the NFB network, so they "think the same", meaning they "agree" on output voltage.
2) nuke the "voltage source" by adding a series resistor so it´s not so any more.
(did I mention bad engineering?)
3) on a practical side, pray those amps are stable, components do not drift, a bad resistor does not need to be replaced in the future, etc.
4) "but ... but .... it´s "only" 0.1 ohm added"
Think again.
I use lots of 0.1 ohm resistors in my designs, both as emitter ballast and in speaker-to-ground current sensors for mixed feedback or current source NFB.
Each and every one of them steals me of 1 Volt when passing 10A, wwhich happens all the time at the power level and loads I use.
Remember it is the Peak current which is the parameter here stealing from my rail voltage, RMS value is irrelevant, except in an indirect way.
5) note: I have nothing against Bridging, which puts voltage sources in series.
there is only one brain deciding on its own voltage out, unconnected to the other voltage source 😉
Except by nothing less than the full load 😱
Nor against paralleling lots of power transistors: they provide the muscle but there is only one brain.
Could write also about parallel transformer windings and parallel batteries, but don´t want to spread too much.
Plus my coffee break is over 😉
The best way to force two circuits to properly share a load is to have one master and one slave (apology to anyone offended by the terms but they are the industry standard) with their outputss tied together. Monitor the current in the master with a resistor in the output and force the current in the slave to be the same.
I'm sure the Neurochrome site is just fine, but there's this other document on bridging and paralleling those chips that you may want to read. I dare say it's as trustworthy as Neurochrome, because it's from the chip manufacturer:
https://www.ti.com/lit/an/snaa021b/snaa021b.pdf
https://www.ti.com/lit/an/snaa021b/snaa021b.pdf