hi everyone
i'm attempting to add a reclocking circuit to my simple tda1543 dac and i'm having a few problems.
i'm using this circuit:
http://pc.watch.impress.co.jp/docs/2004/1005/nidac_ah7.jpg
its a very simple reclocking circuit, but i'm a newbie so its a start!
anyway, i have built the circuit and wired it to to dac BUT i'm getting A LOT of noise and static. music is barely hearable over the noise.
i'm using the 74hc4040n from philips and a 11.2896mhz XO
thanks for reading!
i'm attempting to add a reclocking circuit to my simple tda1543 dac and i'm having a few problems.
i'm using this circuit:
http://pc.watch.impress.co.jp/docs/2004/1005/nidac_ah7.jpg
its a very simple reclocking circuit, but i'm a newbie so its a start!
anyway, i have built the circuit and wired it to to dac BUT i'm getting A LOT of noise and static. music is barely hearable over the noise.
i'm using the 74hc4040n from philips and a 11.2896mhz XO
thanks for reading!
Looks to me like you are trying to asynchronously reclock S/PDIF input at a fixed clock rate equal to the master clock rate. This will not work because the crystal frequency will not exactly match the rate of the data stream, it's only close. Close is not good enough. Also, there seems to be an error in your schematic.
The only way that asynchronous reclocker will work is if the fixed-clock frequency is higher, such as an upsampler chip, and there must be logic to add the new data sample points to the data stream.
The clock that you are using is not synchronous with the data stream, so it cannot be used to clock the stream. This will not work even if there is a large data "FIFO" added to store the data. Eventually, there will be a data overrun or underrun and data will be lost, resulting in pops and dropouts.
Steve N.
Empirical Audio
Manufacturer
The only way that asynchronous reclocker will work is if the fixed-clock frequency is higher, such as an upsampler chip, and there must be logic to add the new data sample points to the data stream.
The clock that you are using is not synchronous with the data stream, so it cannot be used to clock the stream. This will not work even if there is a large data "FIFO" added to store the data. Eventually, there will be a data overrun or underrun and data will be lost, resulting in pops and dropouts.
Steve N.
Empirical Audio
Manufacturer
thanks for the reply 🙂
the schematic i posted is similar to what Doede Douma uses in his DDDAC, so i guess that the circuit should work.
http://pc.watch.impress.co.jp/docs/2004/1005/nishikawa.htm
http://www.dddac.de/
i just had a look over the the circuit of my CS8141 and i noticed that SEL (pin16) and M0 (pin23) is grounded (which means set to LOW, please correct me if i'm wrong, trying to learn all this stuff 🙂). whereas in both the Japanese and dddac schematic shows SEL and M0 being set to high on the 5V supply.
could this be the cause of all the noise and static that i'm hearing? i will work on this later when i get home. i will lift pin16 and pin23 off ground and connect them to the 5V line.
the schematic i posted is similar to what Doede Douma uses in his DDDAC, so i guess that the circuit should work.
http://pc.watch.impress.co.jp/docs/2004/1005/nishikawa.htm
http://www.dddac.de/
i just had a look over the the circuit of my CS8141 and i noticed that SEL (pin16) and M0 (pin23) is grounded (which means set to LOW, please correct me if i'm wrong, trying to learn all this stuff 🙂). whereas in both the Japanese and dddac schematic shows SEL and M0 being set to high on the 5V supply.
could this be the cause of all the noise and static that i'm hearing? i will work on this later when i get home. i will lift pin16 and pin23 off ground and connect them to the 5V line.
one more observation...
in one of Deode's schematics it says to use Q1 and Q7 of the 74HC4040 to obtain the 2.8224mhz and 44.1khz, respectively.
but then in another one of his schematics it says to use Q2 and Q8.
which is the correct one?
in one of Deode's schematics it says to use Q1 and Q7 of the 74HC4040 to obtain the 2.8224mhz and 44.1khz, respectively.
but then in another one of his schematics it says to use Q2 and Q8.
which is the correct one?
The I2S outputs from the CS8412 must be high-impedance state for this to work properly, otherwise the CS8412 is driving the ripple-counter 4040 outputs and there wil be contention.
BTW - I still stand by my conclusion. This is a non-deterministic design. The data being clocked into the D/A chip cannot be predicted because the clock from the 4040 is not synchronous with the CS8412 data stream. Sometimes it will be the correct data that gets clocked into the D/A chip and other times it will not. It may also go metastable inside the D/A chip and not resolve properly. It can take several clock cycles to resolve properly. This is what happens when you clock data into a flip-flop without meeting the specified setup and hold times.
The TDA1545A for instance, requires 12nsec minimum data set-up time and 2nsec minimum hold time, and that is with a synchronous clock.
Steve N.
Empirical Audio
EE with 30 years digital design experience
BTW - I still stand by my conclusion. This is a non-deterministic design. The data being clocked into the D/A chip cannot be predicted because the clock from the 4040 is not synchronous with the CS8412 data stream. Sometimes it will be the correct data that gets clocked into the D/A chip and other times it will not. It may also go metastable inside the D/A chip and not resolve properly. It can take several clock cycles to resolve properly. This is what happens when you clock data into a flip-flop without meeting the specified setup and hold times.
The TDA1545A for instance, requires 12nsec minimum data set-up time and 2nsec minimum hold time, and that is with a synchronous clock.
Steve N.
Empirical Audio
EE with 30 years digital design experience
thanks for the reply Steve! 🙂
it will take me a bit of time to absorb all the info you have posted! but thank you for helping me out.
do you have any recommendations for a method or diy kit that i could try play around with for reclocking?
it will take me a bit of time to absorb all the info you have posted! but thank you for helping me out.
do you have any recommendations for a method or diy kit that i could try play around with for reclocking?
thanks for the link Fin!
i know steve told me the circuit would produce pops and clicks, but i tried it anyway (no harm done).
so i have the music playing now and there is no loud static or noise but there are those little pops and clicks in the background.
so how does Doede pull it off in his dac?
i know steve told me the circuit would produce pops and clicks, but i tried it anyway (no harm done).
so i have the music playing now and there is no loud static or noise but there are those little pops and clicks in the background.
so how does Doede pull it off in his dac?
it sounds quite good actually.
not sure if it's placebo or not, but everything sounds more detailed and open, there is a bit more '3D-ness' as well.
not sure if it's placebo or not, but everything sounds more detailed and open, there is a bit more '3D-ness' as well.
Fin said:
oh that's right!
i actually work in sunnybank pineland shopping cetnre, just down the road!
Its not the best way to reclock with a 4040, better choice would be dividers like 74HC163. If i have time will search comments here on diyaudio about that issue
tubee said:
thanks for the tip, i'll do a bit more reading on it. but it seems i will have to you use 2 of them to get the right divider, i will do some reading on how to do that.
do you think it will stop the clicking and popping noises?
rfbrw said:
i did a little search and so far i can tell that his not a fan paralleling 8 tda1543 chips 🙄
but will do more reading
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