help with Kwak-clock

I build my own kwak-clock using vero board.

Elso, sent me the PCB graphic and the circuit schematics.

I downloaded the j309 datasheet and the pin arrangement is

pin1 = drain
pin2 = source
pin3 = gate

Looking the PCB graphic and circuit schematics, it seems that on the PCB graphic, the j309 orientation is

pin1 = drain
pin2 = gate
pin3 = source

Can someone comfirmed that the PCB is incorrect based on the schematics? Maybe I was wrong. Please suggest.

Thank you.

jayel
 
KWAK-CLOCK FET Pin out

Hi jayel,
I did not make the PCB layout. I got these from Vitaly, I believe.
I no longer have any of these pictures due to a computercrash, caused by a virus. Thank you idiot, lunatic out there for designing and spreading this virus nonsense!
The datasheet shows the correct pinout. Source is the center pin.
Can you send back to me the PCB layouts? I will have a look into it. On the other hand Vitaly has reported to me his circuit is working fine.
;)
To answer your last post the 68pF is connected between gate & source and the 39pF between source & ground.;)
Hope this helps.
 
You're right about the 68/39 caps. I made a mistake.

I just sent you the PCB graphic. If you have a look at the schematics and the PCB, the 10pf silver mica (the one connected to the crystal) is connected to source which is wrong if you have a look at the schematics. I'll also send you the schematics.

If this PCB works then possibly the schematics is wrong. In the PCB, the 10pF silver mica is connected to source then the crystal is then connected to the other lead of the capacitor and ground.

Also as it is, the PCB is definitely wrong as the gate is connected to ground. There should be some white in between in the 1kohm resistor.

Well, thanks for the reply Elso.

Jayel

ps. Has the schematic graphic been changed before? As I made the circuit using the schematic and have only looked at the PCB when the circuit doesn't seem to work.
 
PCB layout

Hi jayel,
You are absolutely right there should be a break under the 1k resistor in the foil pattern. Otherwise the <b>source</B> of the FET is grounded; not the gate. I think the orientation of the FET is correct. Please bear in mind the PCB is seen fom the topside(componentside)
I got several PCB layouts for the KWAK-CLOCK sent to me and usually don't review them for faults.;)
The <B>schematic</B> for the KWAK-CLOCK is correct.:)

I see the problem. This PCB layout was probably made for the earlier version of the KWAK-CLOCK using the 2SK117BL FET. This FET has a different pinout. I am sorry for the confusion.:eek: