Hello everyone, I'm new to the audio world. This is my first practical assignment for my courses so i want to improve it more. Since English is not my mother language and this is my first question so maybe there are some mistakes.
The requirement of the circuit:
This circuit i adapted from Audio power amplifier design handbook of Douglas. However, when i tried to simulate this, i met some problem:
thank you verry muchh.
The requirement of the circuit:
- The bandwidth: 15-50Khz
- Output power on load should > 30W
- The efficiency η > 45%
- Distortion < 1% at 1Khz
- Input signal is in range 50mV - 100mV.
- The input resistance: Rin > 20k
This circuit i adapted from Audio power amplifier design handbook of Douglas. However, when i tried to simulate this, i met some problem:
- The quiescence current is too high, about 130mA through Q15 when a load is attached (if no load, floating, the ide current is much lower). I changed the bias voltage with Vbe Multiplier (Q10) but it didn't help.
- The gain to fulfill input 100mV and output 30W which make it become tremendous ~ R8/R9. So i think i need a preamplifier before feed the signal into power amplifier.
thank you verry muchh.
Your "idle" current most likely is due to the amplifier's large output offset voltage. 900mV/8 ohms is over 100mA. You need to improve the open-loop circuit balance. I suspect the current source in your VAS (Q6+Q9) is nowhere near the current needed to result in low output offset voltage.
For starters, remove the 8 ohm load and see how the circuit behaves. Adjust resistor values to minimize the output offset voltage. Only then can you be sure that your idle current really IS idle current.
It shouldn't be necessary to use a preamplifier to achieve the target gain.
For starters, remove the 8 ohm load and see how the circuit behaves. Adjust resistor values to minimize the output offset voltage. Only then can you be sure that your idle current really IS idle current.
It shouldn't be necessary to use a preamplifier to achieve the target gain.
I did not look to carefully, but Q18 is essentially cutoff. Not sure why. Vb is -1.08 and Ve is higher, -.936 Vb should be around -.2 ish.
Another thing is the major mismatch in R to gnd of the input pair. The input side sees 33K to gnd while the feedback has 250K. Just out of curiosity try setting R5 to 250K. That will balance the bias current voltage at the input pair. I've no idea what your model is saying the 2907 beta is good for. Specs if I remember right are anything from 100 to around 300+.
The gain seems way too high, which would also cause excessive output DC offset.
Shouldn't the R8 value of 250k be more like 25k, or maybe 33k to balance the input currents?
The sensitivity requirement of 100mV is not representative of current design practice, which is more like 1.5V - 2V for rated output.
Shouldn't the R8 value of 250k be more like 25k, or maybe 33k to balance the input currents?
The sensitivity requirement of 100mV is not representative of current design practice, which is more like 1.5V - 2V for rated output.
You have DC offset on the output because R8 is WAY too big. You have about -1V on the output that needs to be fed back to the LTP in order to correct the offset. But you lose all that voltage across R8 due to the base current on Q5. Even if that base current is only 4uA, 4e-6*2.5e5=1V, so lose all that DC feedback and the LTP can't correct the voltage. If you absolutely need that much gain, make both R8 and R9 smaller.
You want to keep R8 and R5 the same value to get close to 0V on the output. R8=R5=47k, R9=220ohm might be a good combination. EDIT: I just tried it in one of my "Blameless clones" (very similar to yours) and the values I just mentioned gave me <1mV on the output and good performance. Give it a shot!
I’m as puzzled as you are, but it’s getting late here in the United States. I’ll have a look tomorrow!
Have you checked whether the frequency response at the input, comming from the signal source, is OK?
Maybe, try other transistors; perhaps one of the simulation models is partially faulty.
I suspect your transistor types (PN...) mean 2N2222 and 2N2907?
Transistors Q8 and Q17, being TO18 types, are running too hot at 300+ mW anyway.
Maybe, try other transistors; perhaps one of the simulation models is partially faulty.
I suspect your transistor types (PN...) mean 2N2222 and 2N2907?
Transistors Q8 and Q17, being TO18 types, are running too hot at 300+ mW anyway.
One thing I can't exactly tell. It looks like you are running an AC analysis. That's fine for small signal stuff, but this is not small signal. So my guess is you ran the AC, where it did the operating point, computed everything for small signal, then ran the sweep. You'll need to run a transient analysis to get valid data since this is not small signal. You'll want to anyway to see what kind of crossover distortion your getting.
I drew it up in LTSpice. I didn't have the exact same models, so the output transistors are different. Also, I didn't keep the same component numbering. I made two changes: I removed the extra transistor from the VAS (Q16 and Q17 in your diagram) so it's no longer a Darlington configuration. Your design had a very pronounced Miller effect that was limiting the bandwidth, so I just simplified it, which got me close to 100kHz bandwidth. This will increase THD a bit, but it's still well below the 1% you stated as a requirement. I also increased the quiescent (bias) current so the output devices draw about 1.8W at idle, which is within the typical range for a 30W amplifier. The gain with 47k/220 gives you almost exactly 30W RMS at 75mV input (if I did the math right).
I think this should be good enough for a homework assignment. I left the rest alone, since you want to hand in YOUR design and not mine. I just helped you with some small adjustments. I hope this helps!
I think this should be good enough for a homework assignment. I left the rest alone, since you want to hand in YOUR design and not mine. I just helped you with some small adjustments. I hope this helps!
...which I believe is why he was getting poor bandwidth, since the Miller cap acted on the combined hFE. I just simplified it down to one transistor. Should be enough for a homework assignment that required 1% THD.